STS1DN45K3
Dual N-channel 450 V, 3.2
Ω,
0.5 A SuperMESH3™
Power MOSFET in SO-8
Preliminary data
Features
Type
STS1DN45K3
■
■
■
V
DSS
450 V
R
DS(on)
max
< 3.8
Ω
I
D
0.5 A
P
w
1.7 W
100% avalanche tested
Low input capacitances and gate charge
Low gate input resistance
Application
■
Switching applications
Description
SuperMESH3™ is a new Power MOSFET
technology that is obtained via improvements
applied to STMicroelectronics’ SuperMESH™
technology combined with a new optimized
vertical structure. The resulting product has an
extremely low on resistance, superior dynamic
performance and high avalanche capability,
making it especially suitable for the most
demanding applications.
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Figure 1.
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SO-8
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Internal schematic diagram
Table 1.
Device summary
Marking
1ll45
Packages
SO-8
Packaging
Tape and reel
Order codes
STS1DN45K3
April 2010
Doc ID 17338 Rev 1
1/10
www.st.com
10
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
Contents
STS1DN45K3
Contents
1
2
3
4
5
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Test circuits
.............................................. 6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
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2/10
Doc ID 17338 Rev 1
STS1DN45K3
Electrical ratings
1
Electrical ratings
Table 2.
Symbol
V
DS
V
GS
I
D
I
D
I
DM (1)
P
TOT
I
AR
E
AS
dv/dt
(2)
T
stg
T
j
Absolute maximum ratings
Parameter
Drain-source voltage (V
GS
= 0)
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C (dual operation)
Total dissipation at T
C
= 25 °C (single operation)
Avalanche current, repetitive or not-repetitive (pulse
width limited by T
j
max)
Single pulse avalanche energy
(starting T
j
= 25°C, I
D
= I
AR
, V
DD
= 50 V)
Peak diode recovery voltage slope
Storage temperature
Value
450
± 30
0.5
0.32
2
1.7
1.3
Unit
V
V
A
A
Max. operating junction temperature
1. Pulse width limited by safe operating area
2. I
SD
≤ 0.5
A, di/dt
≤
TBD A/µs, V
Peak
< V
(BR)DSS
Table 3.
Symbol
Thermal data
b
O
et
l
so
R
thj-amb(1)
ro
P
e
Thermal resistance junction-amb max
(single operation)
Thermal resistance junction-amb max
(dual operation)
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(s
t
b
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so
te
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r
P
d
o
0.5
TBD
TBD
150
uc
s)
t(
A
W
W
A
mJ
V/ns
°C
°C
- 55 to 150
Parameter
Value
62.5
78
Unit
°C/W
°C/W
1. When mounted on FR4 board (steady state)
Doc ID 17338 Rev 1
3/10
Electrical characteristics
STS1DN45K3
2
Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Table 4.
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
On /off states
Parameter
Drain-source
breakdown voltage
Test conditions
I
D
= 1 mA, V
GS
= 0
Min.
450
1
50
Typ.
Max.
Unit
V
µA
µA
V
DS
= Max rating
Zero gate voltage
drain current (V
GS
= 0) V
DS
= Max rating, T
C
=125 °C
Gate-body leakage
current (V
DS
= 0)
V
GS
= ± 20 V
Gate threshold voltage V
DS
= V
GS
, I
D
= 50 µA
Static drain-source on
resistance
V
GS
= 10 V, I
D
= 0.5 A
Table 5.
Symbol
C
iss
C
oss
C
rss
(1)
Dynamic
Parameter
Input capacitance
Output capacitance
Reverse transfer
capacitance
Equivalent
capacitance time
related
Test conditions
C
o(tr)
bs
O
et
l
o
C
o(er)(2)
ro
P
e
R
G
Q
g
Q
gs
Q
gd
uc
d
s)
t(
V
DS
=25 V, f = 1 MHz,
V
GS
= 0
O
-
so
b
te
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ro
P
Min.
-
3
uc
d
3.75
3.2
Typ.
150
30
6
±10
4.5
3.8
s)
t(
µA
V
Ω
Max.
Unit
pF
pF
pF
-
-
V
DS
= 0 to 360 V, V
GS
= 0
-
TBD
-
pF
Equivalent
capacitance energy
related
Intrinsic gate
resistance
Total gate charge
Gate-source charge
Gate-drain charge
TBD
-
pF
f = 1 MHz open drain
V
DD
= 360 V, I
D
= 0.5 A,
V
GS
= 10 V
(see
Figure 3)
-
TBD
6
TBD
TBD
-
Ω
nC
nC
nC
-
-
1. Time related is defined as a constant equivalent capacitance giving the same charging time as C
oss
when
V
DS
increases from 0 to 80% V
DSS
2. Energy related is defined as a constant equivalent capacitance giving the same stored energy as C
oss
when V
DS
increases from 0 to 80% V
DSS
4/10
Doc ID 17338 Rev 1
STS1DN45K3
Electrical characteristics
Table 6.
Symbol
t
d(on)
t
r
t
d(off)
t
f
Switching times
Parameter
Turn-on delay time
Rise time
Turn-off-delay time
Fall time
Test conditions
V
DD
= 225 V, I
D
= 0.5 A,
R
G
= 4.7
Ω,
V
GS
= 10 V
(see
Figure 4)
Min.
Typ.
TBD
TBD
TBD
TBD
Max
Unit
ns
ns
ns
ns
-
-
Table 7.
Symbol
I
SD
I
SDM
(1)
Source drain diode
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
SD
= 0.5 A, V
GS
= 0
I
SD
= 0.5 A, di/dt = 100 A/µs
V
DD
= 100 V (see
Figure 7)
I
SD
= 0.5 A, di/dt = 100 A/µs
V
DD
= 100 V, T
j
= 150 °C
(see
Figure 7)
Test conditions
Min.
-
Typ.
V
SD (2)
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Table 8.
Symbol
BV
GSO
Gate-source Zener diode
Parameter
Test conditions
Igs=± 1 mA (open drain)
Min.
30
Typ.
Max. Unit
V
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o
The built-in back-to-back Zener diodes have specifically been designed to enhance not only
the device’s ESD capability, but also to make them safely absorb possible voltage transients
that may occasionally be applied from gate to source. In this respect the Zener voltage is
appropriate to achieve an efficient and cost-effective intervention to protect the device’s
integrity. These integrated Zener diodes thus avoid the usage of external components
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(s
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-
-
-
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d
TBD
TBD
TBD
TBD
TBD
TBD
s)
t(
0.5
2
1.6
Max. Unit
A
A
V
ns
nC
A
ns
nC
A
Gate-source breakdown
voltage
Doc ID 17338 Rev 1
5/10
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