DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD8873
(5400
×
5400) PIXELS
×
3 COLOR CCD LINEAR IMAGE SENSOR
DESCRIPTION
The
µ
PD8873 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to
electrical signal and has the function of color separation.
The
µ
PD8873 has 3 rows of (5400 + 5400) staggered pixels, and each row has a dual-sided readout-type charge
transfer register. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for
1200 dpi/A4 color image scanners, color facsimiles and so on.
FEATURES
•
Valid photocell
•
Photocell pitch
•
Line spacing
•
Color filter
•
Resolution
: (5400 + 5400) staggered pixels
×
3
: 5.25
µ
m
: 63
µ
m (12 lines) Red line - Green line, Green line - Blue line
10.5
µ
m (2 lines) Odd line - Even line (for each color)
: Primary colors (red, green and blue), pigment filter (with light resistance 10 lx•hour)
: 48 dot/mm A4 (210
×
297 mm) size (shorter side)
1200 dpi US letter (8.5”
×
11”) size (shorter side)
•
Drive clock level : CMOS output under 5 V operation
•
Data rate
•
Power supply
•
On-chip circuits
: 12.5 MHz Max.
: +12 V
: Reset feed-through level clamp circuits
Voltage amplifiers
7
ORDERING INFORMATION
Part Number
Package
CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
µ
PD8873CY
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S16614EJ2V0DS00 (2nd edition)
Date Published July 2003 NS CP (K)
Printed in Japan
2003
µ
PD8873
BLOCK DIAGRAM
V
OD
20
φ
SEL
19
GND GND
2
11
φ
2
17
φ
2
15
φ
1
14
CCD analog shift register
Transfer gate
S10800
D14
D64
D66
D65
D67
13
D68
Transfer gate
CCD analog shift register
CCD analog shift register
Transfer gate
S10800
D66
D65
D67
S1
V
OUT
1
21
(Blue)
φ
TG1
(Blue)
S2
······
Photocell
(Blue)
12
D68
S1
V
OUT
2
22
(Green)
D14
D64
φ
TG2
(Green)
S2
······
Photocell
(Green)
Transfer gate
CCD analog shift register
CCD analog shift register
Transfer gate
S10800
D14
D64
D66
D65
D67
10
D68
Transfer gate
CCD analog shift register
4
3
S1
V
OUT
3
(Red)
φ
TG3
(Red)
S2
1
······
Photocell
(Red)
5
9
8
φ
CLB
φ
R
φ
1
φ
2
φ
1
2
Data Sheet S16614EJ2V0DS
µ
PD8873
PIN CONFIGURATION (Top View)
CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
•
µ
PD8873CY
Output signal 3 (Red)
Ground
Reset gate clock
Reset feed-through level clamp clock
Shift register clock 1
No connection
No connection
Shift register clock 1
Shift register clock 2
Transfer gate clock 3
(for Red)
Ground
V
OUT
3
GND
1
2
22
21
V
OUT
2
V
OUT
1
V
OD
Output signal 2 (Green)
Output signal 1 (Blue)
Output drain voltage
dpi selector
No connection
Shift register clock 2
No connection
Shift register clock 2
Shift register clock 1
Transfer gate clock 1
(for Blue)
Transfer gate clock 2
(for Green)
1
1
φ
R
φ
CLB
φ
1
NC
NC
3
4
5
6
7
8
9
10
11
1
20
19
18
17
16
15
14
13
12
φ
SEL
NC
Green
Blue
Red
φ
2
NC
φ
1
φ
2
φ
2
φ
1
φ
TG1
φ
TG2
10800
10800
GND
Caution Connect the No connection pins (NC) to GND.
10800
φ
TG3
Data Sheet S16614EJ2V0DS
3
µ
PD8873
PHOTOCELL STRUCTURE DIAGRAM
2.75
µ
m
5.25
µ
m
2.5
µ
m
Channel stopper
Aluminum
shield
PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing)
5.25
µ
m
5.25
µ
m
5.25
µ
m
Blue photocell array
Blue photocell array
2 lines
(10.5
µ
m)
10 lines
(52.5
µ
m)
12 lines
(63
µ
m)
5.25
µ
m
5.25
µ
m
5.25
µ
m
Green photocell array
Green photocell array
2 lines
(10.5
µ
m)
10 lines
(52.5
µ
m)
12 lines
(63
µ
m)
5.25
µ
m
5.25
µ
m
5.25
µ
m
Red photocell array
Red photocell array
2 lines
(10.5
µ
m)
4
Data Sheet S16614EJ2V0DS
µ
PD8873
ABSOLUTE MAXIMUM RATINGS (T
A
=
+25°C)
Parameter
Output drain voltage
Shift register clock voltage
Reset gate clock voltage
Reset feed-through level clamp clock voltage
dpi select signal voltage
Transfer gate clock voltage
Operating ambient temperature
Storage temperature
Note
Symbol
V
OD
V
φ
1
, V
φ
2
V
φ
R
V
φ
CLB
V
φ
SEL
V
φ
TG1
to V
φ
TG3
T
A
T
stg
Ratings
−0.3
to
+15
−0.3
to
+8
−0.3
to
+8
−0.3
to
+8
−0.3
to
+8
−0.3
to
+8
0 to
+60
−40
to
+70
Unit
V
V
V
V
V
V
°C
°C
Note
Use at the condition without dew condensation.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (T
A
=
+25°C)
Parameter
Output drain voltage
Shift register clock high level
Shift register clock low level
Reset gate clock high level
Reset gate clock low level
Reset feed-through level clamp clock high level
Reset feed-through level clamp clock low level
dpi select signal high level
dpi select signal low level
Transfer gate clock high level
Transfer gate clock low level
Data rate
Clock pulse frequency
V
OD
V
φ
1H
, V
φ
2H
V
φ
1L
, V
φ
2L
V
φ
RH
V
φ
RL
V
φ
CLBH
V
φ
CLBL
V
φ
SELH
V
φ
SELL
V
φ
TG1H
to V
φ
TG3H
V
φ
TG1L
to V
φ
TG3L
f
φ
R
f
φ
1
, f
φ
2
Symbol
Min.
11.4
4.75
0
4.75
0
4.75
0
4.75
0
4.75
0
−
−
Typ.
12.0
5.0
0
5.0
0
5.0
0
5.0
0
V
φ
1H
0
2.0
2.0
Note
Max.
12.6
5.5
0.15
5.5
0.15
5.5
0.15
5.5
0.15
V
φ
1H
Note
Unit
V
V
V
V
V
V
V
V
V
V
V
MHz
MHz
0.15
12.5
12.5
Note
When Transfer gate clock high level (V
φ
TG1H
to V
φ
TG3H
) is higher than Shift register clock high level (V
φ
1H
),
Image lag can increase.
Data Sheet S16614EJ2V0DS
5
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