v1.1
IGLOO Low-Power Flash FPGAs
with Flash*Freeze Technology
Features and Benefits
Low Power
•
•
•
•
•
1.2 V to 1.5 V Core Voltage Support for Low Power
Supports Single-Voltage System Operation
5 µW Power Consumption in Flash*Freeze Mode
Low-Power Active FPGA Operation
Flash*Freeze Technology Enables Ultra-Low Power
Consumption while Maintaining FPGA Content
• Easy Entry to / Exit from Ultra-Low-Power Flash*Freeze
Mode
®
Advanced I/O
•
•
•
•
•
•
•
•
•
•
•
700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)
1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages—up to 4 Banks per Chip
Single-Ended
I/O
Standards:
LVTTL,
LVCMOS
3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X
1
, and
LVCMOS 2.5 V / 5.0 V Input
1
Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS
(AGL250 and above)
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold-Sparing I/Os
‡
Programmable Output Slew Rate
1
and Drive Strength
Weak Pull-Up/-Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages across the IGLOO Family
1
High Capacity
• 15 k to 1 Million System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/Os
Reprogrammable Flash Technology
•
•
•
•
130-nm, 7-Layer Metal, Flash-Based CMOS Process
Live-at-Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design When Powered Off
Clock Conditioning Circuit (CCC) and PLL
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption (except ARM
®
-enabled IGLOO
®
devices) via JTAG (IEEE 1532–compliant)
1
• FlashLock
®
to Secure FPGA Contents
• Six CCC Blocks, One with an Integrated PLL
• Configurable
Phase
Shift, Multiply/Divide,
Delay
Capabilities, and External Feedback
• Wide Input Frequency Range (1.5 MHz up to 250 MHz)
Embedded Memory
• 1 kbit of FlashROM User Nonvolatile Memory
1
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
1
• True Dual-Port SRAM (except ×18)
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
ARM Processor Support in IGLOO FPGAs
• M1 IGLOO Devices—Cortex™-M1 Soft Processor Available
with or without Debug
AGL060
60 k
512
1,536
10
18
4
1k
Yes
1
18
2
96
CS121
QN132
3
VQ100
FG144
3
AGL125
125 k
1,024
3,072
16
36
8
1k
Yes
1
18
2
133
CS196
QN132
VQ100
FG144
AGL250
M1AGL250
250 k
–
6,144
24
36
8
1k
Yes
1
18
4
143
CS196
5
QN132
3,5
VQ100
FG144
AGL600
M1AGL600
600 k
–
13,824
36
108
24
1k
Yes
1
18
4
235
CS281
FG144,
FG256,
FG484
AGL1000
M1AGL1000
1M
–
24,576
53
144
32
1k
Yes
1
18
4
300
CS281
FG144, FG256,
FG484
IGLOO Product Family
IGLOO Devices
ARM-Enabled IGLOO Devices
System Gates
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
Flash*Freeze Mode (typical, µW)
RAM kbits (1,024 bits)
4,608-Bit Blocks
FlashROM Bits
Secure (AES) ISP
4
Integrated PLL in CCCs
VersaNet Globals
1
I/O Banks
Maximum User I/Os
Package Pins
CS
QFN
VQFP
FBGA
AGL015
15 k
128
384
5
–
–
1k
–
–
6
2
49
AGL030
30 k
256
768
5
–
–
1k
–
–
6
2
81
UC81, CS81
QN132
VQ100
QN68
Notes:
1. Six chip (main) and twelve quadrant global networks are available for AGL060 and above.
2. For higher densities and support of additional features, refer to the
IGLOOe Low-Power Flash FPGAs with Flash*Freeze
Technology
handbook.
3. Device/package support TBD.
4. AES is not available for ARM-enabled IGLOO devices.
5. The M1AGL250 device does not support this package.
1 AGL015 and AGL030 devices do not support this feature.
July 2008
© 2008 Actel Corporation
‡ Supported only by AGL015 and AGL030 devices.
I
IGLOO Low-Power Flash FPGAs
I/Os Per Package
1
IGLOO Devices
ARM-Enabled IGLOO Devices
AGL015
AGL030
AGL060
AGL125
AGL250
M1AGL250
2, 3
I/O Type
Differential I/O Pairs
Differential I/O Pairs
Differential I/O Pairs
–
–
–
–
–
–
–
25
44
53
74
FG484
23 × 23
529
1.0
2.23
Single-Ended I/O
2
Single-Ended I/O
2
Single-Ended I/O
2
–
–
–
–
–
–
–
97
177
215
300
289
1.0
1.60
AGL600
M1AGL600
AGL1000
M1AGL1000
Single-Ended I/O
Single-Ended I/O
Single-Ended I/O
Package
QN68
UC81
CS81
CS121
VQ100
QN132
CS196
FG144
FG256
CS281
FG484
Notes:
49
–
–
–
–
–
–
–
–
–
–
–
66
66
–
77
81
–
–
–
–
–
–
–
–
96
71
80
8
–
96
8
–
–
–
Single-Ended I/O
–
–
–
–
71
84
133
97
–
–
–
–
–
–
–
68
87
8
143
97
–
–
–
–
–
–
–
13
19
8
30
24
–
–
–
–
–
–
–
–
–
–
97
177
215
235
–
–
–
–
–
–
–
25
43
53
60
1. When considering migrating your design to a lower- or higher-density device, refer to the
IGLOO Low-Power Flash
FPGAs
handbook to ensure compliance with design and board migration requirements.
2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
3. The M1AGL250 device does not support QN132 or CS196 packages. Refer to the
IGLOO Low-Power Flash FPGAs
handbook for position assignments of the 15 LVPECL pairs.
4. FG256 and FG484 are footprint-compatible packages.
5. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of
single-ended user I/Os available is reduced by one.
6. "G" indicates RoHS-compliant packages. Refer to
"IGLOO Ordering Information" on page III
for the location of the "G"
in the part number.
7. Device/package support TBD.
IGLOO FPGAs Package Sizes Dimensions
Package
Length
×
(mm\mm)
Nominal Area
(mm
2
)
Pitch (mm)
Height (mm)
UC81
Width
4 × 4
16
0.4
0.80
CS81
5
×
5
25
0.5
0.80
CS121
6×6
36
0.5
0.99
QN68
8×8
64
0.4
0.90
QN132
8×8
64
0.5
0.75
CS196
8×8
64
0.5
1.20
CS281
10 × 10
100
0.5
1.05
FG144
13 × 13
169
1.0
1.45
VQ100
14 × 14
196
0.5
1.00
FG256
17 × 17
II
v1.1
IGLOO Low-Power Flash FPGAs
IGLOO Ordering Information
AGL1000
V2
_
FG
G
144
I
Application (Temperature Range)
Blank =
Commercial
(0°C to +70°C Ambient Temperature)
I = Industrial (
–
40°C to +85°C Ambient Temperature)
PP = Pre-Production
ES = Engineering
Sample
(Room Temperature Only)
Package Lead
Count
Lead-Free Packaging
Blank =
Standard
Packaging
G=
RoHS-Compliant Packaging
Package Type
UC = Micro
Chip Scale
Package (0.4 mm pitch)
CS
=
Chip Scale
Package (0.4 mm and 0.5 mm pitches)
QN = Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitch)
VQ = Very Thin Quad Flat Pack (0.5 mm pitch)
FG = Fine Pitch Ball
Grid
Array (1.0 mm pitch)
Speed Grade
F = 20%
Slower
than
Standard*
Blank =
Standard
Supply
Voltage
2 = 1.2 V to 1.5 V
5 = 1.5 V only
Part Number
IGLOO Devices
AGL015 = 15,000
System Gates
AGL030 = 30,000
System Gates
AGL060 =
60,000 System Gates
AGL125 = 125,000
System Gates
AGL250 = 250,000
System Gates
AGL600 =
600,000 System Gates
AGL1000 = 1,000,000
System Gates
IGLOO Devices with Cortex-M1
M1AGL250 = 250,000
System Gates
M1AGL600 =
600,000 System Gates
M1AGL1000= 1,000,000
System Gates
Notes:
1. Marking Information: IGLOO V2 devices do not have V2 marking, but IGLOO V5 devices are marked accordingly.
2. The DC and switching characteristics for the –F speed grade targets are based only on simulation.
The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some
restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only
supported in the commercial temperature range.
v1.1
III
IGLOO Low-Power Flash FPGAs
Temperature Grade Offerings
AGL015
Package
QN68
UC81
CS81
CS121
VQ100
QN132
CS196
FG144
FG256
CS281
FG484
Notes:
1. C = Commercial temperature range: 0°C to 70°C ambient temperature.
2. I = Industrial temperature range: –40°C to 85°C ambient temperature.
3. Device/package support TBD.
4. The M1AGL250 device does not support FG256 or QN132 packages.
C, I
–
–
–
–
–
–
–
–
–
–
–
C, I
C, I
–
C, I
C, I
–
–
–
–
–
–
–
–
C, I
C, I
C, I
3
–
C, I
3
–
–
–
–
–
–
–
C, I
C, I
C, I
C, I
–
–
–
AGL030
AGL060
AGL125
AGL250
M1AGL250
4
–
–
–
–
C, I
C, I
3
C, I
C, I
–
–
–
AGL600
M1AGL600
–
–
–
–
–
–
–
C, I
C, I
C, I
C, I
AGL1000
M1AGL1000
–
–
–
–
–
–
–
C, I
C, I
C, I
C, I
Speed Grade and Temperature Grade Matrix
Temperature Grade
C
2
I
3
Notes:
1. The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some
restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only
supported in the commercial temperature range.
2. C = Commercial temperature range: 0°C to 70°C ambient temperature.
3. I = Industrial temperature range: –40°C to 85°C ambient temperature.
References made to IGLOO devices also apply to ARM-enabled IGLOOe devices. The ARM-enabled part numbers start with
M1 (Cortex-M1).
Contact your local Actel representative for device availability:
http://www.actel.com/contact/default.aspx.
–F
1
Std.
✓
–
✓
✓
AGL015 and AGL030
The AGL015 and AGL030 are architecturally compatible; there are no RAM or PLL features.
IV
v1.1
1 – IGLOO Device Family Overview
General Description
The IGLOO family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a
single-chip solution, small footprint packages, reprogrammability, and an abundance of advanced
features.
The Flash*Freeze technology used in IGLOO devices enables entering and exiting an ultra-low-
power mode that consumes as little as 5 µW while retaining SRAM and register data. Flash*Freeze
technology simplifies power management through I/O and clock management with rapid recovery
to operation mode.
The Low Power Active capability (static idle) allows for ultra-low-power consumption (from 12 µW)
while the IGLOO device is completely functional in the system. This allows the IGLOO device to
control system power management based on external inputs (e.g., scanning for keyboard stimulus)
while consuming minimal power.
Nonvolatile flash technology gives IGLOO devices the advantage of being a secure, low power,
single-chip solution that is live at power-up (LAPU). IGLOO is reprogrammable and offers time-to-
market benefits at an ASIC-level unit cost.
These features enable designers to create high-density systems using existing ASIC or FPGA design
flows and tools.
IGLOO devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as
clock conditioning circuitry based on an integrated phase-locked loop (PLL). The AGL015 and
AGL030 devices have no PLL or RAM support. IGLOO devices have up to 1 million system gates,
supported with up to 144 kbits of true dual-port SRAM and up to 300 user I/Os.
M1 IGLOO devices support the high-performance, 32-bit Cortex-M1 processor developed by ARM
for implementation in FPGAs. Cortex-M1 is a soft processor that is fully implemented in the FPGA
fabric. It has a three-stage pipeline that offers a good balance between low-power consumption
and speed when implemented in an M1 IGLOO device. The processor runs the ARMv6-M instruction
set, has a configurable nested interrupt controller, and can be implemented with or without the
debug block. Cortex-M1 is available for free from Actel for use in M1 IGLOO FPGAs.
The ARM-enabled devices have Actel ordering numbers that begin with M1AGL and do not support
AES decryption.
Flash*Freeze Technology
The IGLOO device offers unique Flash*Freeze technology, allowing the device to enter and exit
ultra-low-power Flash*Freeze mode. IGLOO devices do not need additional components to turn off
I/Os or clocks while retaining the design information, SRAM content, and registers. Flash*Freeze
technology is combined with in-system programmability, which enables users to quickly and easily
upgrade and update their designs in the final stages of manufacturing or in the field. The ability of
IGLOO V2 devices to support a wide range of core voltage (1.2 V to 1.5 V) allows further reduction
in power consumption, thus achieving the lowest total system power.
When the IGLOO device enters Flash*Freeze mode, the device automatically shuts off the clocks
and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and
data is retained.
The availability of low-power modes, combined with reprogrammability, a single-chip and single-
voltage solution, and availability of small-footprint, high pin-count packages, make IGLOO devices
the best fit for portable electronics.
v1.1
1-1
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