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Datasheet> All Categories > storage> storage> STK15C88-WF25
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STK15C88-WF25

Description
Non-Volatile SRAM, 32KX8, 25ns, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28
Categorystorage    storage   
File Size294KB，10 Pages
ManufacturerSimtek
Websitehttp://www.simtek.com
Environmental Compliance
Download Datasheet Parametric Compare View All

STK15C88-WF25 Overview

Non-Volatile SRAM, 32KX8, 25ns, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28

STK15C88-WF25 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerSimtek
package instructionDIP, DIP28,.6
Reach Compliance Codeunknown
ECCN codeEAR99
Maximum access time25 ns
JESD-30 codeR-PDIP-T28
JESD-609 codee3
length36.83 mm
memory density262144 bit
Memory IC TypeNON-VOLATILE SRAM
memory width8
Number of functions1
Number of terminals28
word count32768 words
character code32000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32KX8
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP28,.6
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
power supply5 V
Certification statusNot Qualified
Maximum seat height4.57 mm
Maximum standby current0.0015 A
Maximum slew rate0.097 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperature40
width15.24 mm

STK15C88-WF25 Preview

STK15C88
32K x 8
AutoStore™
nvSRAM
QuantumTrap™
CMOS
Nonvolatile Static RAM
FEATURES
• Nonvolatile Storage without Battery Problems
• Directly Replaces 32K x 8 Static RAM, Battery-
Backed RAM or EEPROM
• 25ns, 35ns and 45ns Access Times
•
STORE
to nonvolatile elements Initiated by
Software or
AutoStore™
•
RECALL
to SRAM Initiated by Software or
Power Restore
• 10mA Typical I
CC
at 200ns Cycle Time
• Unlimited READ, WRITE and
RECALL
Cycles
• 1,000,000
STORE
Cycles to nonvolatile ele-
ments
• 100-Year Data Retention in nonvolatile ele-
ments (Commercial/Industrial)
• Single 5V
+
10% Operation
• Commercial and Industrial Temperatures
• 28-Pin PDIP and SOIC Packages
DESCRIPTION
The STK15C88 is a fast
SRAM
with a nonvolatile
element incorporated in each static memory cell.
The
SRAM
can be read and written an unlimited
number of times, while independent nonvolatile data
resides in nonvolatile elements. Data transfers from
the
SRAM
to the nonvolatile elements (the
STORE
operation) can take place automatically on power
down using charge stored in system capacitance.
Transfers from the nonvolatile elements to the
SRAM
(the
RECALL
operation) take place automatically on
restoration of power. Initiation of
STORE
and
RECALL
cycles can also be controlled by entering specific
read sequences. The STK15C88 is pin-compatible
with 32k x 8
SRAM
s and battery-backed
SRAM
s,
allowing direct substitution while enhancing perfor-
mance. A similar device (STK16C88) with an inter-
nally integrated capacitor is available for
applications with very fast power-down slew rates.
The STK14C88, which uses an external capacitor, is
another alternative for these applications.
BLOCK DIAGRAM
QUANTUM TRAP
512 x 512
PIN CONFIGURATIONS
V
CC
STORE/
RECALL
CONTROL
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
ROW DECODER
STORE
STATIC RAM
ARRAY
512 x 512
RECALL
POWER
CONTROL
SOFTWARE
DETECT
INPUT BUFFERS
COLUMN I/O
COLUMN DEC
A
0
- A
13
V
CC
W
A
13
A
8
A
9
A
11
G
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
28 - 300 PDIP
28 - 600 PDIP
28 - 300 SOIC
28 - 350 SOIC
PIN NAMES
A
0
- A
14
W
Address Inputs
Write Enable
Data In/Out
Chip Enable
Output Enable
Power (+ 5V)
Ground
A
0
A
1
A
2
A
3
A
4
A
10
DQ
0
- DQ
7
G
E
W
E
G
V
CC
V
SS
September 2003
1
Document Control # ML0016 rev 0.1
STK15C88
ABSOLUTE MAXIMUM RATINGS
a
Voltage on Input Relative to Ground . . . . . . . . . . . . . .–0.5V to 7.0V
Voltage on Input Relative to V
SS
. . . . . . . . . . –0.6V to (V
CC
+ 0.5V)
Voltage on DQ
0-7
. . . . . . . . . . . . . . . . . . . . . . –0.5V to (V
CC
+ 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . . 15mA
Note a: Stresses greater than those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at conditions
above those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
DC CHARACTERISTICS
SYMBOL
I
CC
b
1
(V
CC
= 5.0V
±
10%)
COMMERCIAL
MIN
MAX
97
80
70
3
10
2
30
25
22
1.5
±1
±5
2.2
V
SS
– .5
2.4
0.4
0
70
– 40
V
CC
+ .5
0.8
2.2
V
SS
– .5
2.4
0.4
85
INDUSTRIAL
MIN
MAX
100
85
70
3
10
2
31
26
23
1.5
±1
±5
V
CC
+ .5
0.8
UNITS
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
V
V
V
V
°C
t
AVAV
= 25ns
t
AVAV
= 35ns
t
AVAV
= 45ns
All Inputs Don’t Care, V
CC
= max
W
≥
(V
CC
– 0.2V)
All Others Cycling, CMOS Levels
All Inputs Don’t Care
t
AVAV
= 25ns, E
≥
V
IH
t
AVAV
= 35ns, E
≥
V
IH
t
AVAV
= 45ns, E
≥
V
IH
E
≥
(V
CC
– 0.2V)
All Others V
IN
≤
0.2V or
≥
(V
CC
– 0.2V)
V
CC
= max
V
IN
= V
SS
to V
CC
V
CC
= max
V
IN
= V
SS
to V
CC
, E or G
≥
V
IH
All Inputs
All Inputs
I
OUT
= – 4mA
I
OUT
= 8mA
NOTES
PARAMETER
Average V
CC
Current
I
CC
c
2
3
Average V
CC
Current during
STORE
Average V
CC
Current at t
AVAV
= 200ns
5V, 25°C, Typical
Average V
CAP
Current during
AutoStore™
Cycle
Average V
CC
Current
(Standby, Cycling TTL Input Levels)
V
CC
Standby Current
(Standby, Stable CMOS Input Levels)
Input Leakage Current
Off-State Output Leakage Current
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
I
CC
b
I
CC
c
4
I
SB
d
1
I
SB
d
2
I
ILK
I
OLK
V
IH
V
IL
V
OH
V
OL
T
A
Note b: I
CC
and I
CC
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
1
3
Note c: I
CC
and I
CC
are the average currents required for the duration of the respective
STORE
cycles (t
STORE
) .
2
4
Note d: E
≥
V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤
5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
5.0V
480 Ohms
OUTPUT
255 Ohms
CAPACITANCE
e
SYMBOL
C
IN
C
OUT
PARAMETER
Input Capacitance
Output Capacitance
(T
A
= 25
°
C, f = 1.0MHz)
MAX
5
7
UNITS
pF
pF
CONDITIONS
∆V
= 0 to 3V
∆V
= 0 to 3V
30 pF
INCLUDING
SCOPE AND
FIXTURE
Note e: These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
September 2003
2
Document Control # ML0016 rev 0.1
STK15C88
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
1
2
3
4
5
6
7
8
9
10
11
#1, #2
t
ELQV
t
AVAV
f
g
(V
CC
= 5.0V
±
10%)
PARAMETER
STK15C88-25
MIN
MAX
25
25
25
10
5
5
10
0
10
0
25
0
35
0
13
0
45
5
5
13
0
15
35
35
15
5
5
15
STK15C88-35
MIN
MAX
35
45
45
20
STK15C88-45
MIN
MAX
45
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Alt.
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
t
AVQV
t
GLQV
t
AXQX
t
ELQX
t
EHQZ
h
t
GLQX
t
GHQZ
h
e
d
,
e
g
t
OHZ
t
PA
t
PS
t
ELICCH
t
EHICCL
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note g: I/O state assumes E, G < V
IL
and W > V
IH
; device is continuously selected.
Note h: Measured + 200mV from steady state output voltage.
SRAM READ CYCLE #1:
Address Controlled
f, g
2
t
AVAV
ADDRESS
5
3
t
AVQV
DATA VALID
t
AXQX
DQ (DATA OUT)
SRAM READ CYCLE #2:
E Controlled
f
2
t
AVAV
ADDRESS
6
1
t
ELQV
1
1
t
EHICCL
7
t
EHQZ
E
t
ELQX
G
8
t
GLQV
4
9
t
GHQZ
t
GLQX
DQ (DATA OUT)
t
ELICCH
I
CC
STANDBY
DATA VALID
10
ACTIVE
September 2003
3
Document Control # ML0016 rev 0.1
STK15C88
SRAM WRITE CYCLES #1 & #2
NO.
12
13
14
15
16
17
18
19
20
21
SYMBOLS
#1
t
AVAV
t
WLWH
t
ELWH
t
DVWH
t
WHDX
t
AVWH
t
AVWL
t
WHAX
t
WLQZ
h, i
t
WHQX
#2
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
Alt.
t
WC
t
WP
t
CW
t
DW
t
DH
t
AW
t
AS
t
WR
t
WZ
t
OW
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
5
PARAMETER
STK15C88-25
MIN
25
20
20
10
0
20
0
0
10
5
MAX
MIN
35
25
25
12
0
25
0
0
13
5
(V
CC
= 5.0V
±
10%)
STK15C88-35
MAX
STK15C88-45
MIN
45
30
30
15
0
30
0
0
15
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note i:
Note j:
If W is low when E goes low, the outputs remain in the high-impedance state.
E or W must be
≥
V
IH
during address transitions.
SRAM WRITE CYCLE #1:
W Controlled
j
12
t
AVAV
ADDRESS
t
ELWH
E
17
t
AVWH
13
t
WLWH
15
t
DVWH
DATA IN
t
WLQZ
DATA OUT
PREVIOUS DATA
HIGH IMPEDANCE
14
19
t
WHAX
18
t
AVWL
W
16
t
WHDX
DATA VALID
20
21
t
WHQX
SRAM WRITE CYCLE #2:
E Controlled
j
12
t
AVAV
ADDRESS
18
t
AVEL
E
14
t
ELEH
19
t
EHAX
17
t
AVEH
W
13
t
WLEH
15
t
DVEH
16
t
EHDX
DATA VALID
HIGH IMPEDANCE
DATA IN
DATA OUT
September 2003
4
Document Control # ML0016 rev 0.1
STK15C88
AutoStore™/POWER-UP RECALL
NO.
22
23
24
25
SYMBOLS
Standard
t
RESTORE
t
STORE
V
SWITCH
V
RESET
Power-up
RECALL
Duration
STORE
Cycle Duration
Low Voltage Trigger Level
Low Voltage Reset Level
4.0
PARAMETER
(V
CC
= 5.0V
±
10%)
STK15C88
MIN
MAX
550
10
4.5
3.6
UNITS NOTES
µs
ms
V
V
k
g
Note k: t
RESTORE
starts from the time V
CC
rises above V
SWITCH
.
AutoStore™/POWER-UP RECALL
V
CC
5V
24
V
SWITCH
25
V
RESET
AutoStore™
23
t
STORE
POWER-UP
RECALL
22
t
RESTORE
W
DQ (DATA OUT)
POWER-UP
RECALL
BROWN OUT
NO
STORE
DUE TO
NO SRAM WRITES
NO
RECALL
(V
CC
DID NOT GO
BELOW V
RESET
)
BROWN OUT
AutoStore™
NO
RECALL
(V
CC
DID NOT GO
BELOW V
RESET
)
BROWN OUT
AutoStore™
RECALL
WHEN
V
CC
RETURNS
ABOVE V
SWITCH
September 2003
5
Document Control # ML0016 rev 0.1
More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

STK15C88-WF25 Related Products

STK15C88-WF25 STK15C88-WF25I STK15C88-PF25I STK15C88-WF45 STK15C88-PF45
Description Non-Volatile SRAM, 32KX8, 25ns, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28 Non-Volatile SRAM, 32KX8, 25ns, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28 Non-Volatile SRAM, 32KX8, 25ns, CMOS, PDIP28, 0.300 INCH, PLASTIC, DIP-28 Non-Volatile SRAM, 32KX8, 45ns, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28 Non-Volatile SRAM, 32KX8, 45ns, CMOS, PDIP28, 0.300 INCH, PLASTIC, DIP-28
Is it Rohs certified? conform to conform to conform to conform to conform to
Maker Simtek Simtek Simtek Simtek Simtek
package instruction DIP, DIP28,.6 DIP, DIP28,.6 DIP, DIP28,.3 DIP, DIP28,.6 DIP, DIP28,.3
Reach Compliance Code unknown unknown unknown unknown unknow
ECCN code EAR99 EAR99 EAR99 EAR99 EAR99
Maximum access time 25 ns 25 ns 25 ns 45 ns 45 ns
JESD-30 code R-PDIP-T28 R-PDIP-T28 R-PDIP-T28 R-PDIP-T28 R-PDIP-T28
JESD-609 code e3 e3 e3 e3 e3
length 36.83 mm 36.83 mm 34.67 mm 36.83 mm 34.67 mm
memory density 262144 bit 262144 bit 262144 bit 262144 bit 262144 bi
Memory IC Type NON-VOLATILE SRAM NON-VOLATILE SRAM NON-VOLATILE SRAM NON-VOLATILE SRAM NON-VOLATILE SRAM
memory width 8 8 8 8 8
Number of functions 1 1 1 1 1
Number of terminals 28 28 28 28 28
word count 32768 words 32768 words 32768 words 32768 words 32768 words
character code 32000 32000 32000 32000 32000
Operating mode ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS
Maximum operating temperature 70 °C 85 °C 85 °C 70 °C 70 °C
organize 32KX8 32KX8 32KX8 32KX8 32KX8
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code DIP DIP DIP DIP DIP
Encapsulate equivalent code DIP28,.6 DIP28,.6 DIP28,.3 DIP28,.6 DIP28,.3
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form IN-LINE IN-LINE IN-LINE IN-LINE IN-LINE
Parallel/Serial PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL
Peak Reflow Temperature (Celsius) 260 260 260 260 260
power supply 5 V 5 V 5 V 5 V 5 V
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 4.57 mm 4.57 mm 4.57 mm 4.57 mm 4.57 mm
Maximum standby current 0.0015 A 0.0015 A 0.0015 A 0.0015 A 0.0015 A
Maximum slew rate 0.097 mA 0.1 mA 0.1 mA 0.07 mA 0.07 mA
Maximum supply voltage (Vsup) 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V
Minimum supply voltage (Vsup) 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V
Nominal supply voltage (Vsup) 5 V 5 V 5 V 5 V 5 V
surface mount NO NO NO NO NO
technology CMOS CMOS CMOS CMOS CMOS
Temperature level COMMERCIAL INDUSTRIAL INDUSTRIAL COMMERCIAL COMMERCIAL
Terminal surface Matte Tin (Sn) Matte Tin (Sn) Matte Tin (Sn) Matte Tin (Sn) Matte Tin (Sn)
Terminal form THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE
Terminal pitch 2.54 mm 2.54 mm 2.54 mm 2.54 mm 2.54 mm
Terminal location DUAL DUAL DUAL DUAL DUAL
Maximum time at peak reflow temperature 40 40 40 40 40
width 15.24 mm 15.24 mm 7.62 mm 15.24 mm 7.62 mm

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Shortcut:   A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

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