Preliminary Data Sheet
July 2006
ET1310
PCI Express
™
Gigabit Ethernet Controller
with
TruePHY
™
Technology
Feature Summary
Media Access Controller (MAC):
— 10/100/1000 Mbits/s triple-speed operation
— Compatible with
IEEE
®
802.3, 802.3u, 802.3x,
802.3ac, 802.1q, and VLAN
— Unicast, multicast, and broadcast address
filtering
— Support for promiscuous mode
—
IEEE
802.3x frame-based flow control
— Prioritized/optimized receive processing
— Optimized cut-through support for lower latency
— Interrupt coalescing
— Jumbo frame support up to 9216 bytes/frame
— PXE 2.0 support
— Wake on LAN
PCI Express
Revision 1.0a[1]* Interface:
— Full compliance with Revision 1.0a
— Single-lane, 2.5 Gbits/s full-duplex channel
— Multiple traffic classes support
— Advanced error reporting
— 64-bit and 32-bit platform support
— End-to-end CRC (ECRC) support
Agere
TruePHY
technology:
— 10Base-T/100Base-TX/1000Base-T gigabit
Ethernet copper transceiver
— Oversampling architecture improves signal
integrity and signal-to-noise ratio
— Automatic speed negotiation and downshift
— UNH interoperability certification
— Dynamic link equalization
— Comprehensive link diagnostics
Software:
—
Windows 98SE
®
, Windows 2000
®
, and
Windows XP
®
32-bit and 64-bit device drivers
—
Linux
®
2.4 and 2.6 drivers
Low power consumption:
— 934 mW in 1000Base-T mode
— ACPI[2]* Rev. 2.0b power management
— Active-state power management for
PCI
Express
Physical:
— 68-pin MLCC package (10 x 10 x 1 mm)
— 0 °C to 70 °C ambient temperature
— Integrated voltage regulator support
— 3.3 V and 2.5 V I/O support
—
IEEE
1149.1 (JTAG)
Description
Agere Systems’ ET1310 provides single-chip net-
work interface solutions for gigabit Ethernet. The
ET1310, optimized for both mobile platforms and
desktop platforms, provides a complete
PCI Express
NIC card and LAN-on-motherboard (LOM) solution
for PC platforms. This device combines a gigabit
Ethernet MAC with Agere gigabit Ethernet
TruePHY
technology and a high-performance, standards-com-
pliant
PCI Express
1.0a host system interface, and
provides true gigabit throughput realized in the indus-
try’s smallest footprint and lowest power consump-
tion. A full suite of software support enables a
smooth transition to
PCI Express
as the industry-
standard host interface.
The ET1310 is targeted at power-conscious mobile
platforms where power management, component
height, extended thermal operating range, and small
footprint are critical. The ET1310 is also targeted at
desktop applications where maximum performance
is key, and power management is less of a concern.
The package offers a compact 10 mm x 10 mm foot-
print, minimizing board space and substantially
reducing the number of signal traces, thereby elimi-
nating design complexity and lowering cost for both
LOM and NIC applications.
Designed specifically for
PCI Express,
the
ET1310 architecture leverages the full capabilities of
the bidirectional 2.5 Gbits/s host system link to
increase throughput, minimize latency, and reduce
on-chip buffering. Multiple traffic classes per virtual
channel on the
PCI Express
link provide native sup-
port for QoS transmission for real-time and multime-
dia applications in a standards-based framework,
ensuring compatibility with current and future operat-
ing systems. Active-state power management allows
dynamic power management during periods of
reduced network activity.
* See Appendix A—References on page 48.
Agere Systems - Proprietary
ET1310
PCI Express
Gigabit Ethernet Controller
with
TruePHY
Technology
Preliminary Data Sheet
July 2006
Table of Contents
(continued)
Contents
Page
Table
Page
Feature Summary ............................................................. 1
Description ........................................................................ 1
Functional Description................................................ 3
PCI Express
Subsystem Block.......................................... 4
Basic Features ........................................................... 4
PCI Express
Enhanced Features............................... 4
Architecture ................................................................ 4
Transaction Layer....................................................... 5
Data Link Layer .......................................................... 5
Physical Layer............................................................ 6
PCI Express
Configuration Block ............................... 9
Host Controller Block ...................................................... 13
System Interface ...................................................... 13
Media Access Controller .......................................... 14
Gigabit Ethernet PHY Block ..................................... 16
Oversampling Architecture....................................... 16
Automatic Speed Downshift ..................................... 16
Transmit Functions................................................... 17
Receive Functions.................................................... 17
Autonegotiation ........................................................ 18
Loopback Mode........................................................ 18
LEDs ........................................................................ 19
Cable Diagnostics .................................................... 19
ET1310 Generic Functions ............................................. 20
Clock and Reset Module (CRM)............................... 20
Power Management ................................................. 21
EEPROM Subsystem ............................................... 29
Pin Information ................................................................ 30
Pin Diagram, 68-Pin MLCC ..................................... 30
Hardware Interfaces................................................. 31
PCI Express
Interface .............................................. 32
EEPROM Interface................................................... 33
Miscellaneous Interface ........................................... 34
LEDs Interface ......................................................... 34
Media-Dependent Interface:
Transformer Interface........................................ 35
Clocking ................................................................... 36
JTAG ........................................................................ 36
Regulator Control ..................................................... 37
Power, Ground, and No Connect ............................. 38
Electrical Specifications .................................................. 39
Absolute Maximum Ratings...................................... 39
Recommended Operating Conditions ...................... 39
Device Electrical Characteristics .............................. 40
Power Consumption ................................................. 41
Timing Specifications................................................ 42
JTAG Timing ............................................................. 42
Crystal Oscillator Clock Timing................................. 43
Powerup Timing ....................................................... 44
Powerdown Timing .................................................. 45
Package Diagram, 68-Pin MLCC .................................... 46
Agere ET1310 IC Marking............................................... 46
Agere Part #: L-ET1310R1B1-M ............................ 46
Ordering Information ....................................................... 47
Related Product Documentation ..................................... 47
Appendix A—References......................................... 48
Table 1. ET1310
PCI
Configuration Space ............................9
Table 2. Cable Diagnostic Functions ...................................19
Table 3. Power Management Capabilities ...........................21
Table 4. Power-States Definition..........................................23
Table 5. Host Controller Subsystem and GbE PHY
in D1 and D3 Power States...............................23
Table 6. Comparison of D3hot, D3warm, and
D3cold States....................................................28
Table 7.
PCI Express
Signal Description .............................32
Table 8. EEPROM Interface ................................................33
Table 9. Miscellaneous Signals ...........................................34
Table 10. LEDs ....................................................................34
Table 11. Transformer Interface Signals ..............................35
Table 12. Clocking ...............................................................36
Table 13. JTAG Test Interface..............................................36
Table 14. Regulator Control Interface..................................37
Table 15. Supply Voltage Combinations ..............................38
Table 16. Power, Ground, and No Connect .........................38
Table 17. Absolute Maximum Ratings .................................39
Table 18. Recommended Operating Conditions..................39
Table 19. Thermal Characteristics .......................................39
Table 20. Device Characteristics—3.3 V Digital
I/O Supply (DVDDIO)........................................40
Table 21. Device Characteristics—2.5 V Digital
I/O Supply (DVDDIO)........................................40
Table 22. PERST_N dc Characteristics ...............................40
Table 23. WAKE_N dc Characteristics ................................40
Table 24. ET1310 Nominal Power Consumption.................41
Table 25. JTAG Timing ........................................................42
Table 26. Crystal Oscillator Clock Timing ............................43
Table 27. Powerup Timing ...................................................44
Table 28. Powerdown Timing...............................................45
Table 29. Chip Set Names and Part Numbers.....................47
Table 30. Related Product Documentation ..........................47
Figure
Page
Figure 1. ET1310 Block Diagram ..........................................3
Figure 2. Host Controller Subsystem Block Diagram ..........13
Figure 3. ET1310
TruePHY
Transceiver
Block Diagram .................................................16
Figure 4. Pin Diagram for ET1310 in 68-Pin
MLCC Package (Top View) .............................30
Figure 5. ET1310 Gigabit Ethernet Card
Block Diagram .................................................31
Figure 6.
PCI Express
Signals.............................................32
Figure 7. EEPROM Interface...............................................33
Figure 8. JTAG Timing ........................................................42
Figure 9. Powerup Timing ...................................................44
Figure 10. Powerdown Timing.............................................45
Figure 11. ET1310 IC Marking Example and
Description.......................................................46
2
Agere Systems - Proprietary
Agere Systems Inc.
Preliminary Data Sheet
July 2006
ET1310
PCI Express
Gigabit Ethernet Controller
with
TruePHY
Technology
The major blocks discussed in the following sections
include:
PCI Express
subsystem
Host Controller subsystem
Gigabit Ethernet PHY
ET1310 generic functions:
— Clock and reset controller
— Power management controller
— EEPROM subsystem (and other hardware inter-
faces)
Description
(continued)
To achieve optimum network I/O performance, the
ET1310 supports simultaneous outstanding split read/
write transactions and out-of-order transfer completion,
which maximize system parallelism and reduces
dependence on host system capabilities.
Functional Description
The ET1310 introduces a new generation of gigabit
Ethernet controllers that provides the combination of
performance, power, and cost attributes that enable
migration to gigabit Ethernet for all mainstream desktop
and notebook applications.
The ET1310 is designed to address high-performance
system requirements for
PCI Express-based
host sys-
tems. Figure 1 shows the main blocks of the ET1310.
PCI Express
SUBSYSTEM
HOST CONTROLLER
SUBSYSTEM
GIGABIT
ETHERNET
PHY
PERST_N
PET_P/N
TX DMA
ENGINE
TRANSACTION LAYER
PHYSICAL LAYER
DATA LINK LAYER
TX
PROCESS
MAC GMII
GbE
PHY
TRD[0:3]±
UTP 5
RX DMA
ENGINE
MEMORY
PCI
EXPRESS
LINK
PER_P/N
REFCLK_P/N
RX
PROCESS
MDIO
LED_ACT
GLOBAL
RESOURCE
MANAGER
LED_LNK
TCK
WAKE_N
CONFIG./MANAGEMENT
HOT
PLUG
CONFIG
SPACE
LINK
PM
SERIAL
EEPROM
CONTROLLER
CLK/RST
CONTROLLER
CLOCK
OSCILLATOR
CLK
RST
JTAG/
TEST
TRST_N
TMS
TDI
TDO
SDA
SCL
LAN_DISABLE
XTAL_1 XTAL_2
Figure 1. ET1310 Block Diagram
Agere Systems Inc.
Agere Systems - Proprietary
3
ET1310
PCI Express
Gigabit Ethernet Controller
with
TruePHY
Technology
Preliminary Data Sheet
July 2006
PCI Express
Subsystem Block
Basic Features
Full compliance with
PCI Express Base Specifica-
tion,
Rev. 1.0a[1]*:
— One-lane (x1) architecture
—
PCI Express
Transaction Layer, Data Link Layer,
and Physical layer
— Credit-based flow control fully supported
Single-lane, 2.5 Gbits/s full-duplex channel
Lane polarity inversion support
Support for EEPROM boot-load of configuration reg-
ister values
Multiple traffic classes support
One virtual channel support
Advanced error reporting
Support for 64-bit and 32-bit memory-mapped
address space and corresponding transactions
Support for two requester application clients (DMA
engines) with round-robin arbitration
Configuration space, including:
— Type 0 (end-point)
PCI Express
configuration
space
—
PCI Express
extended capabilities
— Independent control of reset for nonsticky register
bits and sticky bits preserved in AUX power
domain
ASPM (active-state power management) support
Software-controlled legacy
PCI
power management
support
In-band beacon and side-band WAKE_N mecha-
nisms support
In-band messaging:
— Power management (PM)
— Power management event (PME)
— Interrupt virtual wires (INTx)
— Error messages
— MSI support if enabled in configuration space
ECRC support
PCI Express
Enhanced Features
The ET1310 implements all of the required capabilities
specified by the
PCI Express Base Specification,
Rev. 1.0a[1].* In addition, the device supports many of
the optional enhanced features recommended in the
specification.
Enhanced features include hot plug and the following
capability structures:
Power management:
— Active-state power management (ASPM)
PCI Express
extended capabilities:
— Advanced error reporting
— Virtual channel
— Device serial number
Architecture
The
PCI Express
subsystem implements the
PCI
Express Base Specification,
Rev. 1.0a[1] layers:
The
PCI Express
Physical Layer is comprised of an
electrical sublayer and logical sublayer. The logical
sublayer comprises the physical coding subsystem
and implements various state machines exercising
the
PCI Express
link training and status protocols.
The Data Link Layer supports processes and proto-
cols for creating a reliable
PCI Express
point-to-point
link.
The Transaction Layer assembles/disassembles
PCI
Express
packets, instantiating
PCI Express
load/
store transactions. It performs the
PCI Express
pack-
ets flow control management functionality as well.
The
PCI Express
subsystem enables the host to read
from and write to device-specific registers via the
PCI
Express
link.
The
PCI Express
receive and transmit blocks are
responsible for transactions between the Host Control-
ler subsystem and the
PCI Express
core logic. They
manage flow control (FC) credits and request IDs and
provide queues and pipelines. They also manage
Transaction Layer Packet (TLP) processing to access
local resources, such as the
PCI Express
configuration
space.
* See Appendix A—References section on page 48.
4
Agere Systems - Proprietary
Agere Systems Inc.
Preliminary Data Sheet
July 2006
ET1310
PCI Express
Gigabit Ethernet Controller
with
TruePHY
Technology
In addition to the performance-oriented features, the
ET1310 also supports a number of optional features to
ensure data integrity and fault identification. Error
detection at both the link level and the end-to-end sys-
tem level are provided by Link CRC and optionally,
End-to-End CRC (ECRC). Data Poisoning is supported
to ensure fault propagation and localization. Poisoned
write transactions received by the ET1310 are dis-
carded and reported as nonfatal, uncorrectable errors if
advanced error reporting is enabled.
Along with these detection capabilities, Advanced Error
Reporting (AER) is supported to provide comprehen-
sive diagnostics capabilities. The ET1310 maintains
statistics for the following AER metrics:
End-to-End CRC errors
Received malformed TLPs
Receiver overflows
Completion time-out
Flow-control protocol errors
PCI Express
Subsystem Block
(continued)
Architecture
(continued)
The Configuration block implements a single-function
PCI Express
device configuration controller. It maps
programmable device registers into
PCI Express
con-
figuration space. The configuration space contained in
the Configuration block can be accessed through a
local bus interface by the ET1310 serial EEPROM con-
troller. It also includes a submodule dealing with
PCI
Express
messages generation and handling.
The power management controller provides the main
control and status for the ET1310 power management
behavior. It includes the state machines and data struc-
tures necessary to set the power management states
and handle power management events.
Transaction Layer
The Transaction Layer block provides a pipelined, split-
transaction communication protocol for data transfer to
and from the host system. This block provides mechan-
isms for differentiating the ordering and processing of
Transaction Layer Packets (TLPs), credit-based flow
control, and end-to-end data integrity checking.
The ET1310 implementation of the Transaction Layer
capitalizes on the high-performance capabilities of
PCI
Express,
and implements many of the optional features
in order to maximize performance and efficiency.
Key features are as follows:
Multiple traffic classes per virtual channel, with inde-
pendent ordering rules per traffic class to reduce
data dependencies and increase throughput.
Each Requestor client (e.g., TX DMA and RX DMA)
can be mapped to a different traffic class, which elim-
inates implicit ordering dependencies between DMA
channels and allows flexible scheduling through the
Root Complex Controller.
Maximum payload size can be set to 256 or 128.
32-bit and 64-bit memory-mapped address spaces
are supported, enabling interoperability with current-
generation, 32-bit mainstream processors as well as
emerging 64-bit platforms.
Data Link Layer
The Data Link Layer (DLL) block is responsible for reli-
ably conveying Transaction Layer Packets (TLPs) sup-
plied by the Transaction Layer across a
PCI Express
link to the other component's Transaction Layer. The
DLL stores outgoing TLPs in case retransmission is
required, checks data integrity for incoming frames,
and issues error indications for error reporting and log-
ging purposes.
The ET1310 buffering scheme allows automatic
retransmission at full rate without stalling due to lack of
retry buffer space. Additionally, this retry buffer sizing
provides a robust mechanism that compensates for a
wide range of L0s exit latencies on the far end of the
link. For example, while the ET1310 supports fast L0s
exit latencies, its retry buffer sizing scheme supports
upstream devices with slow L0s exit latencies.
Agere Systems Inc.
Agere Systems - Proprietary
5
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