A0800APS3C datasheet, PDF - EEWORLD Datasheet

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A0800APS3C: DescriptionMicroprocessor, 32-Bit, 800MHz, CMOS, CPGA462, STAGGERED, CERAMIC, PGA-453; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，90 Pages; ManufacturerAMD; Websitehttp://www.amd.com

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A0800APS3C Overview

Microprocessor, 32-Bit, 800MHz, CMOS, CPGA462, STAGGERED, CERAMIC, PGA-453

A0800APS3C Parametric

Parameter Name	Attribute value
Maker	AMD
Parts packaging code	PGA
package instruction	IPGA,
Contacts	453
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Address bus width	15
bit size	32
boundary scan	YES
maximum clock frequency	133 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-CPGA-P462
length	49.53 mm
low power mode	YES
Number of terminals	462
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	IPGA
Package shape	SQUARE
Package form	GRID ARRAY, INTERSTITIAL PITCH
Certification status	Not Qualified
Maximum seat height	3.422 mm
speed	800 MHz
Maximum supply voltage	1.85 V
Minimum supply voltage	1.65 V
Nominal supply voltage	1.7 V
surface mount	NO
technology	CMOS
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
width	49.53 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR

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Preliminary Information

AMD Athlon

Processor Model 4

Data Sheet

Publication #

23792

Rev:

Issue Date:

March 2001

Preliminary Information

23792H—March 2001

AMD Athlon™ Processor Model 4 Data Sheet

Contents

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1

AMD Athlon™ Processor Model 4 Microarchitecture

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Signaling Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Push-Pull (PP) Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

AMD Athlon System Bus Signals . . . . . . . . . . . . . . . . . . . . . . . 6

Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1

2.2

2.3

2.4

Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.1

Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Working State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Stop Grant States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Probe State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Connect and Disconnect Protocol . . . . . . . . . . . . . . . . . . . . . . 12

Connect Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Connect State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2

4.3

Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

CPUID Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.1

7.2

7.3

7.4

7.5

7.6

7.7

7.8

7.9

7.10

7.11

7.12

7.13

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Interface Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Voltage Identification (VID[4:0]) . . . . . . . . . . . . . . . . . . . . . . 24

Frequency Identification (FID[3:0]) . . . . . . . . . . . . . . . . . . . . 24

VCCA AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . 25

Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

VCC_CORE Voltage and Current . . . . . . . . . . . . . . . . . . . . . . 27

SYSCLK and SYSCLK# AC and DC Characteristics . . . . . . 28

AMD Athlon System Bus AC and DC Characteristics . . . . . 30

General AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . 32

APIC Pins AC and DC Characteristics . . . . . . . . . . . . . . . . . . 34

Contents

iii

Preliminary Information

AMD Athlon™ Processor Model 4 Data Sheet

23792H—March 2001

Signal and Power-Up Requirements . . . . . . . . . . . . . . . . . . . . 35

8.1

Power-Up Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Signal Sequence and Timing Description . . . . . . . . . . . . . . . . 35

Clock Multiplier Selection (FID[3:0]) . . . . . . . . . . . . . . . . . . . 37

Serial Initialization Packet (SIP) Protocol . . . . . . . . . . . . . . . 38

Processor Warm Reset Requirements . . . . . . . . . . . . . . . . . . 38

The AMD Athlon Processor Model 4 and Northbridge

Reset Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Die Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Socket Tabs for Heatsink Clips . . . . . . . . . . . . . . . . . . . . . . . . 42

Pin Diagram and Pin Name Abbreviations . . . . . . . . . . . . . . 45

Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Detailed Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

A20M# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

AMD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

AMD Athlon System Bus Pins . . . . . . . . . . . . . . . . . . . . . . . . . 62

Analog Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

APIC Pins, PICCLK, PICD[1:0]# . . . . . . . . . . . . . . . . . . . . . . . 62

CLKFWDRST Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

CLKIN, RSTCLK (SYSCLK) Pins. . . . . . . . . . . . . . . . . . . . . . . 62

CONNECT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

COREFB and COREFB# Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 63

CPU_PRESENCE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

DBRDY and DBREQ# Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

FERR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

FID[3:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

FLUSH# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

IGNNE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

INIT# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

INTR Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

K7CLKOUT and K7CLKOUT# Pins. . . . . . . . . . . . . . . . . . . . . 65

Key Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

NC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

NMI Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

PGA Orientation Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

PLL Bypass and Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

PWROK Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

SADDIN[1:0]# and SADDOUT[1:0]# Pins . . . . . . . . . . . . . . . . 66

Scan Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

SCHECK[7:0]# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

SMI# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

STPCLK# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

8.2

Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9.1

9.2

9.3

9.4

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

10.1

10.2

10.3

Contents

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