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Datasheet> All Categories > logic> logic> IDTQS52805TSO
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IDTQS52805TSO

Description
Low Skew Clock Driver, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, SOIC-20
Categorylogic    logic   
File Size94KB，6 Pages
ManufacturerIDT (Integrated Device Technology)
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IDTQS52805TSO Overview

Low Skew Clock Driver, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, SOIC-20

IDTQS52805TSO Parametric

Parameter NameAttribute value
MakerIDT (Integrated Device Technology)
Parts packaging codeSOIC
package instructionSOP,
Contacts20
Reach Compliance Codeunknown
Input adjustmentSCHMITT TRIGGER
JESD-30 codeR-PDSO-G20
JESD-609 codee0
length12.8 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Number of functions2
Number of inverted outputs
Number of terminals20
Actual output times5
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE WITH SERIES RESISTOR
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
propagation delay (tpd)6.5 ns
Certification statusNot Qualified
Same Edge Skew-Max（tskwd）0.9 ns
Maximum seat height2.65 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
width7.5 mm

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Download Datasheet
QS52805T/AT
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
GUARANTEED LOW SKEW
CMOS CLOCK
DRIVER/BUFFER
FEATURES:
−
−
10 output, low skew signal buffer
Guaranteed low skew:
•
0.7ns output skew (same bank)
•
0.9ns output skew (different bank)
•
1ns part-to-part skew
25Ω on-chip resistors available for low noise
Input hysteresis for better noise margin
Monitor output
Undershoot clamp diodes on all inputs
Std. and A speed grades
Available in QSOP and SOIC packages
QS52805T/AT
ADVANCE
INFORMATION
DESCRIPTION
The QS52805T clock buffer/driver circuits can be used for clock buffering
schemes where low skew is a key parameter. This device offers two banks
of five non-inverting outputs. This device provides low propagation delay
buffering with on-chip skew of 0.7ns for same-transition, same-bank signals.
The QS52805T has on-chip series termination resistors for lower noise
clock signals. The QS52805T series resistor version is recommended for
driving unterminated lines with capacitive loading and other noise sensitive
clock distribution circuits. These clock buffer products are designed for use
in high-performance workstations and in embedded and personal comput-
ing systems. Several devices can be used in parallel or scattered throughout
a system for guaranteed low skew, system-wide clock distribution networks.
The QS52805T is characterized for operation at -40°C to +85°C.
−
−
−
−
−
−
FUNCTIONAL BLOCK DIAGRAM
OE
A
5
IN
A
OA
5
OA
1
MON
5
IN
B
OB
5
OB
1
OE
B
NOTE:
This device has 25Ω series termination resistors on each clock output including monitor.
INDUSTRIAL TEMPERATURE RANGE
1
c
1999
Integrated Device Technology, Inc.
AUGUST 2000
DSC-5480/-

IDTQS52805TSO Related Products

IDTQS52805TSO IDTQS52805TQ IDTQS52805TQ8 IDTQS52805ATQ IDTQS52805ATQ8 IDTQS52805ATSO8 IDTQS52805ATSO
Description Low Skew Clock Driver, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, SOIC-20 Low Skew Clock Driver, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, QSOP-20 Low Skew Clock Driver, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, QSOP-20 Low Skew Clock Driver, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, QSOP-20 Low Skew Clock Driver, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, QSOP-20 Low Skew Clock Driver, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, SOIC-20 Low Skew Clock Driver, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO20, SOIC-20
Parts packaging code SOIC QSOP QSOP QSOP QSOP SOIC SOIC
package instruction SOP, SSOP, SSOP, SSOP, SSOP, SOP, SOP,
Contacts 20 20 20 20 20 20 20
Reach Compliance Code unknown unknown unknown unknown unknown unknown unknown
Input adjustment SCHMITT TRIGGER SCHMITT TRIGGER SCHMITT TRIGGER SCHMITT TRIGGER SCHMITT TRIGGER SCHMITT TRIGGER SCHMITT TRIGGER
JESD-30 code R-PDSO-G20 R-PDSO-G20 R-PDSO-G20 R-PDSO-G20 R-PDSO-G20 R-PDSO-G20 R-PDSO-G20
JESD-609 code e0 e0 e0 e0 e0 e0 e0
length 12.8 mm 8.6614 mm 8.6614 mm 8.6614 mm 8.6614 mm 12.8 mm 12.8 mm
Logic integrated circuit type LOW SKEW CLOCK DRIVER LOW SKEW CLOCK DRIVER LOW SKEW CLOCK DRIVER LOW SKEW CLOCK DRIVER LOW SKEW CLOCK DRIVER LOW SKEW CLOCK DRIVER LOW SKEW CLOCK DRIVER
Number of functions 2 2 2 2 2 2 2
Number of terminals 20 20 20 20 20 20 20
Actual output times 5 5 5 5 5 5 5
Maximum operating temperature 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C
Output characteristics 3-STATE WITH SERIES RESISTOR 3-STATE WITH SERIES RESISTOR 3-STATE WITH SERIES RESISTOR 3-STATE WITH SERIES RESISTOR 3-STATE WITH SERIES RESISTOR 3-STATE WITH SERIES RESISTOR 3-STATE WITH SERIES RESISTOR
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SOP SSOP SSOP SSOP SSOP SOP SOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE SMALL OUTLINE
propagation delay (tpd) 6.5 ns 6.5 ns 6.5 ns 5.8 ns 5.8 ns 5.8 ns 5.8 ns
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Same Edge Skew-Max（tskwd） 0.9 ns 0.9 ns 0.9 ns 0.9 ns 0.9 ns 0.9 ns 0.9 ns
Maximum seat height 2.65 mm 1.7272 mm 1.7272 mm 1.7272 mm 1.7272 mm 2.65 mm 2.65 mm
Maximum supply voltage (Vsup) 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V
Minimum supply voltage (Vsup) 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V
Nominal supply voltage (Vsup) 5 V 5 V 5 V 5 V 5 V 5 V 5 V
surface mount YES YES YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal surface TIN LEAD TIN LEAD TIN LEAD TIN LEAD TIN LEAD TIN LEAD TIN LEAD
Terminal form GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
Terminal pitch 1.27 mm 0.635 mm 0.635 mm 0.635 mm 0.635 mm 1.27 mm 1.27 mm
Terminal location DUAL DUAL DUAL DUAL DUAL DUAL DUAL
width 7.5 mm 3.9116 mm 3.9116 mm 3.9116 mm 3.9116 mm 7.5 mm 7.5 mm
Maker IDT (Integrated Device Technology) - - IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)

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