340S14-U datasheet, PDF - EEWORLD Datasheet

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Low-Noise Matched

Transistor Array ICs

THAT

300 Series

FEATURES

• 4 Matched NPN Transistors

º 300 typical h

fe

of 100

º 300A minimum h

fe

of 150

º 300B minimum h

fe

of 300

APPLICATIONS

• Low Noise Front Ends

• Microphone Preamplifiers

• Log/Antilog Amplifiers

• Current Sources

• Current Mirrors

• Multipliers

• 4 Matched PNP Transistors

º 320 typical h

fe

of 75

• 2 Matched PNP and 2 Matched NPN

Transistors

º 340 PNP typical h

fe

of 75

º 340 NPN typical h

fe

of 100

• Low Voltage Noise

º 0.75 nV/

√Hz

(PNP)

º 0.8 nV/

√Hz

(NPN)

• High Speed

º f

T

= 350 MHz (NPN)

º f

T

= 325 MHz (PNP)

• 500

μV

matching between devices

• Dielectrically Isolated for low crosstalk

and high DC isolation

• 36V V

CEO

Description

The THAT 300, 320 and 340 are large

geometry, 4-transistor, monolithic NPN and/or PNP

arrays. They exhibit both high speed and low noise,

with excellent parameter matching between transis-

tors of the same gender. Typical base-spreading

resistance is 25

Ω

for the PNP devices (30

Ω

for the

low-gain NPNs), so their resulting voltage noise is

under 1 nV/√Hz. This makes the 300 series ideally

suited for low-noise amplifier input stages, log ampli-

fiers, and many other applications. The four-NPN

transistor array is available in versions selected for

h

fe

with minimums of 150 (300A) or 300 (300B).

Fabricated in a dielectrically isolated, comple-

mentary bipolar process, each transistor is electri-

cally insulated from the others by a layer of

insulating oxide (not the reverse-biased PN junctions

used in conventional arrays). As a result, they exhibit

inter-device crosstalk and DC isolation similar to

that of discrete transistors. The resulting low

collector-to-substrate capacitance produces a typical

NPN f

T

of 350 MHz (325 MHz for the PNPs).

Substrate biasing is not required for normal opera-

tion, though the substrate should be ac-grounded to

optimize speed and minimize crosstalk.

An eight-transistor bare-die array with similar

performance characteristics (the THAT 380G) is also

available from THAT Corporation. Please contact us

directly or through your local distributor for more

information. Military-grade temperature range

packages are available from TT Semiconductor (see

www.ttsemiconductor.com for more information).

Part Number

300P14-U

300S14-U

300AS14-U

300BS14-U

320P14-U

320S14-U

340P14-U

340S14-U

Configuration

4-Matched NPN Transistors, Beta = 60 min.

4-Matched NPN Transistors, Beta = 150 min.

4-Matched NPN Transistors, Beta = 300 min.

4-Matched PNP Transistors

2-Matched NPN Transistors and

2-Matched PNP Transistors

Table 1. Ordering Information

Package

DIP14

SO14

DIP14

SO14

DIP14

SO14

THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA

Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com

Document 600041 Rev 02

Page 2 of 5

THAT 300 Series Transistor Array ICs

THAT 300

1

2

Q1

3

4

5

6

Q3

7

Q4

8

7

SUB

Q2

12

11

10

9

3

4

5

6

14

13

1

2

THAT 320

14

13

Q1

Q2

12

SUB

11

10

9

Q3

Q4

8

7

3

4

5

6

1

2

THAT 340

14

13

Q1

Q2

12

SUB

11

10

9

Q3

Q4

8

Figure 1. 300 Pinout

Figure 2. 320 Pinout

Figure 3. 340 Pinout

SPECIFICATIONS

1

Absolute Maximum Ratings

2,3

NPN Collector-Emitter Voltage (BV

CEO

)

NPN Collector-Base Voltage (BV

CBO

)

PNP Collector-Emitter Voltage (BV

CEO

)

PNP Collector-Base Voltage (BV

CBO

)

Collector-Substrate Voltage (BV

CS

)

36 V

36V

–36 V

±

100 V

Collector Current

Emitter Current

Operating Temperature Range (T

OP

)

Maximum Junction Temperature (T

JMAX

)

Storage Temperature (T

ST

)

30 mA

-40 to +85 °C

+125 °C

-45 to +125 °C

NPN Electrical Characteristics

2

Parameter

Symbol

Conditions

V

CB

= 10 V, I

C

= 1 mA

I

C

= 10

µA

V

CB

= 10V, I

C

= 1mA

V

CB

= 10V, I

C

= 1 mA, 1kHz

I

C

= 1 mA, V

CB

= 10V

I

C

= 1 mA

I

C

= 10 mA

I

C

= 1 mA

I

C

= 10

μA

V

CB

= 25 V

V

CB

= 0V, 10

μA

< I

C

< 10mA

V

CB

= 10 V, I

C

= 1 mA

I

C

= 1 mA, I

B

= 100μA

300 / 340(Q1,Q2)

Min Typ Max

60

—

100

4

0.8

350

0.5

500

5

25

2

30

0.05

—

3

—

1500

—

Min

150

—

300A

Typ

—

4

0.9

350

0.5

200

2

25

2

TBD

0.05

Max

—

3

—

600

—

Min

300

—

300B

Typ

—

4

1

350

0.5

100

1

25

2

TBD

0.05

Units

Max

—

3

—

300

—

%

nV√Hz

MHz

mV

nA

pA

Ω

V

NPN Current gain

NPN Current Gain Matching

NPN Noise Voltage Density

NPN Gain-Bandwidth Product

NPN

ΔV

BE

300: |V

BE1

-V

BE2

| ; |V

BE3

-V

BE4

|

340: |V

BE1

-V

BE2

|

NPN

ΔI

B

300: |I

B1

-I

B2

| ; |I

B3

-I

B4

|

340: |I

B1

-I

B2

|

NPN Collector-Base Leakage

Current

NPN Bulk Resistance

NPN Base Spreading Resistance

NPN Collector Saturation Voltage

h

fe

Δh

fe

e

N

f

T

V

OS

I

OS

I

CBO

r

BE

r

bb

V

CE(SAT)

THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA

Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com

THAT 300 Series Transistor Array ICs

Page 3 of 5

Document 600041 Rev 02

SPECIFICATIONS

1

(Cont’d)

NPN Electrical Characteristics

2

(cont’d)

Parameter

NPN Output Capacitance

NPN Breakdown Voltage

Input Capacitance

Symbol

C

OB

BV

CEO

C

EBO

Conditions

V

CB

= 10V, I

E

= 0mA, 100kHz

I

C

= 10

μAdc,

I

B

= 0

I

C

= 0 mA, V

EB

= 0 V

300 / 340(Q1,Q2)

Min

Typ Max

—

36

—

3

40

5

—

Min

—

36

—

300A

Typ

3

40

5

Max

—

Min

—

36

—

300B

Typ

3

40

5

Units

Max

—

pF

V

pF

PNP Electrical Characteristics

2

Parameter

PNP Current Gain

Symbol

h

fe

Conditions

V

CB

= -10 V

I

C

= -1 mA

I

C

= -10

μA

V

CB

= -10 V, I

C

= -1 mA

V

CB

= -10 V, I

C

= -1 mA, 1 kHz

I

C

= -1 mA, V

CB

= -10 V

I

C

= -1 mA

I

C

= -10

μA

I

C

= -1 mA

I

C

= -10

μA

V

CB

= -25 V

r

BE

r

bb

V

CE(SAT)

C

OB

BV

CEO

C

EBO

V

CB

= 0 V, -10μA > I

C

> -10 mA

V

CB

= -10 V, I

C

= -1 mA

I

C

= -1 mA, I

B

= -100

μA

V

CB

= -10 V, I

E

= 0 mA, 100 kHz

I

C

= -10 mAdc, I

B

= 0

I

C

= 0 mA, V

EB

= 0 V

Min

50

—

-36

—

Typ

75

5

0.75

325

0.5

700

7

–25

2

25

–0.05

3

-40

6

Max

—

3

—

1800

—

%

nV√Hz

MHz

mV

nA

pA

Ω

V

pF

V

pF

Units

PNP Current Gain Matching

PNP Noise Voltage Density

PNP Gain-Bandwidth Product

PNP

ΔV

BE

320: |V

BE1

-V

BE2

| ; |V

BE3

-V

BE4

|

340: |V

BE1

-V

BE2

|

PNP

ΔI

B

320: |I

B1

-I

B2

| ; |I

B3

-I

B4

|

340: |I

B1

-I

B2

|

Δh

fe

e

N

f

T

V

OS

I

OS

PNP Collector-Base Leakage Current I

CBO

PNP Bulk Resistance

PNP Base Spreading Resistance

PNP Collector Saturation Voltage

PNP Output Capacitance

PNP Breakdown Voltage

Input Capacitance

1. All specifications are subject to change without notice.

2. Unless otherwise noted, T

A

= 25ºC.

3. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only; the

functional operation of the device at these or any other conditions above those indicated in the operational sections of this sp ecification is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA

Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com

Document 600041 Rev 02

Page 4 of 5

THAT 300 Series Transistor Array ICs

Packaging and Soldering Information

The THAT 300, 320 and 340 are available in 14-pin

PDIP and 14-pin surface mount (SOIC) packages.

Package dimensions are shown below.

The 300-series packages are entirely lead-free. The

lead-frames are copper, plated with successive layers of

nickel, palladium, and gold. This approach makes it

possible to solder these devices using lead-free and lead-

bearing solders.

Neither the lead-frames nor the plastic mold

compounds used in the 300-series contains any hazard-

ous substances as specified in the European Union's

Directive on the Restriction of the Use of Certain Hazard-

ous Substances in Electrical and Electronic Equipment

2002/95/EG of January 27, 2003. The surface-mount

package is suitable for use in a 100% tin solder process.

Package Characteristics

Parameter

Through-hole package

Thermal Resistance

θ

JA

Symbol

Conditions

See Fig. 4 for dimensions

DIP package soldered to board

Complies with January 27, 2003 RoHS requirements

See Fig. 5 for dimensions

θ

JA

SO package soldered to board

14 Pin SOP

100

JEDEC JESD22-A113-D (250 ºC)

MSL Above-referenced JEDEC soldering profile

1

Complies with RoHS requirements

ºC/W

Typ

14 Pin PDIP

100

ºC/W

Units

Environmental Regulation Compliance

Surface mount package

Thermal Resistance

Soldering Reflow Profile

Moisture Sensitivity Level

Environmental Regulation Compliance

0.750±0.004

(19.05±0.10)

1

0.25±.004

(6.35±0.10)

0.050

(1.27)

Typ

0.060

(1.52)

Typ.

0.30 ±0.02

(7.62 ±0.5)

0.125±0.004

(3.18±0.10)

0.157 0.245

(3.99) (6.2)

Max Max

1

0.018 (0.46)

Max

0.344 (8.74)

Max

0.069

(1.75)

Max

0.018

(0.46)

0.10 Typ.

(2.54)

0.075

(1.91)

0.010

(0.25)

0.010

(0.25)

Max

Figure 4. Dual-In-Line Package Outline

Figure 5. Surface-Mount Package Outline

THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA

Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com

THAT 300 Series Transistor Array ICs

Page 5 of 5

Document 600041 Rev 02

THAT Corporation believes all the information furnished in this data sheet is accurate and reliable. However we assume

no responsibility for its use nor for any infringements of third-party intellectual property which may result from its use.

LIFE SUPPORT POLICY

THAT Corporation ICs are not designed for use in life support equipment where a malfunction of our ICs might

reasonably result in injury or death. Customers who use or sell our ICs for such life suport application do so at their

own risk, and shall hold THAT Corporation harmless from any and all claims, damages, suits, or expenses resulting

from such use or sale.

CAUTION: THIS IS AN ESD (ELECTROSTATIC DISCHARGE) SENSITIVE DEVICE

Electrostatic charges in the range of several kV can accumulate on the human body as well as test and assembly equip-

ment. This device can be damaged by the currents generated by electrostatic discharge from bodies and equipment.

Moreover, the transistors in this device are unprotected in order to maximize performance and flexibility. Accordingly,

they are more sensitive to ESD damage than many other ICs which include protection devices at their inputs. Note that

all of the pins are susceptible.

Use ESD-preventative measures when storing and handling this device. Unused devices should be stored in conductive

packaging. Packaging should be discharged to the destination socket before the devices are removed from their

packages. ESD damage can occur to these devices even after they are installed in a board-level assembly. Circuits

should include specific and appropriate ESD protection.

Revision History

Revision

00

01

02

ECO

—

2393

2460

Date

April 2004

April 2010

Sept. 2010

Changes

Release

Changed Max. Operating Temperature from 70 °C to

85 °C.

-Added high h

fe

versions Models 300A and 300B with

accompanying specifications and information.

-Revised Features, Applications, and Description sections

-Revised Maximum Rating section

-Added NPN Breakdown Voltage spec.

-Added PNP Breakdown Voltage spec.

-Added Packaging Characteristics Table.

-Revised disclaimer text

2

—

1

2

3

4

5

Page

THAT and

c

are registered trademarks of THAT Corporation.

THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA

Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com

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