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SY10EL07ZI

Description
XOR/XNOR Gate, 10EL Series, 1-Func, 2-Input, ECL, PDSO8, 0.150 INCH, SOIC-8
Categorylogic    logic   
File Size49KB,4 Pages
ManufacturerMicrel ( Microchip )
Websitehttps://www.microchip.com
Download Datasheet Parametric View All

SY10EL07ZI Overview

XOR/XNOR Gate, 10EL Series, 1-Func, 2-Input, ECL, PDSO8, 0.150 INCH, SOIC-8

SY10EL07ZI Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMicrel ( Microchip )
Parts packaging codeSOIC
package instruction0.150 INCH, SOIC-8
Contacts8
Reach Compliance Codenot_compliant
series10EL
JESD-30 codeR-PDSO-G8
JESD-609 codee0
length4.93 mm
Logic integrated circuit typeXOR/XNOR GATE
Humidity sensitivity level1
Number of functions1
Number of entries2
Number of terminals8
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristicsOPEN-EMITTER
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP8,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)240
power supply-5.2 V
Maximum supply current (ICC)17 mA
Prop。Delay @ Nom-Sup0.435 ns
propagation delay (tpd)0.395 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height1.73 mm
surface mountYES
technologyECL
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width3.94 mm
2-INPUT
XOR/XNOR
SY10EL07
SY100EL07
FINAL
FEATURES
s
260ps propagation delay
s
High bandwidth output transitions
s
Internal 75K
input pull-down resistors
s
Available in 8-pin SOIC package
DESCRIPTION
The SY10/100EL07 are 2-input XOR/XNOR gates.
These devices are functionally equivalent to the E107
devices, with higher performance capabilities. With
propagation delays and output transition times
significantly faster than the E107, the EL07 is ideally
suited for those applications which require the ultimate
in AC performance.
PIN CONFIGURATION/BLOCK DIAGRAM
PIN NAMES
Pin
Function
Data Inputs
Data Outputs
NC
D
0
D
1
NC
1
2
3
4
8
7
6
5
V
CC
Q
Q
V
EE
D
0
, D
1
Q
SOIC
TOP VIEW
Rev.: E
Amendment: /0
1
Issue Date: August, 1998
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