DV74LS51N datasheet, PDF - EEWORLD Datasheet

DV74LS51N: DescriptionAND-OR-Invert Gate, LS Series, 2-Func, 6-Input, TTL, PDIP14, PLASTIC, DIP-14; Categorylogic logic; File Size290KB，2 Pages; ManufacturerAVG [AVG Semiconductors(HITEK)]

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DV74LS51N Overview

AND-OR-Invert Gate, LS Series, 2-Func, 6-Input, TTL, PDIP14, PLASTIC, DIP-14

Parameter Name	Attribute value
Maker	AVG [AVG Semiconductors(HITEK)]
Parts packaging code	DIP
package instruction	DIP, DIP14(UNSPEC)
Contacts	14
Reach Compliance Code	unknown
Other features	ASYMMETRICAL I/PS
series	LS
JESD-30 code	R-PDIP-T14
length	18.86 mm
Load capacitance (CL)	15 pF
Logic integrated circuit type	AND-OR-INVERT GATE
MaximumI(ol)	0.008 A
Number of functions	2
Number of entries	6
Number of terminals	14
Maximum operating temperature	70 °C
Minimum operating temperature	-10 °C
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP14(UNSPEC)
Package shape	RECTANGULAR
Package form	IN-LINE
power supply	5 V
Maximum supply current (ICC)	2.8 mA
Prop。Delay @ Nom-Sup	20 ns
propagation delay (tpd)	20 ns
Certification status	Not Qualified
Schmitt trigger	NO
Maximum seat height	4.69 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	TTL
Temperature level	COMMERCIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	7.62 mm

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