FD5T Series
Programmable
CMOS Clock Oscillator
November 2008
• Pletronics’ FD5T Series is a quartz crystal
controlled precision square wave generator with a
programmable CMOS output
• Output frequency from 12 KHz to 230 MHZ
• Selectable low jitter or spread spectrum output.
• Device characteristics may be either factory or
field programmable
• 1.8V, 2.5 or 3.3V LVCMOS outputs
Vdd 1.8V (5)
Vddout
(6)
Reference
oscillator
optional
Voltage
controlled
• 3.2 x 5 mm LCC Ceramic Package
•
Low power
• This is a low cost, mass produced oscillator.
• Tape and Reel or cut tape packaging is
available.
• Designed for high density SMD needs
• Excellent frequency stability options
Optional
Vcontrol
S2/SCL (1)
S1/SDA (2)
Ground (3)
PLL Multiplier #1
optional
Spread Spectrum
optional
Bypass Mode
MUX #1
Divider #1
/1 to /1023
Y1
(4)
Out
- Programming
control
- eePROM
- SDA/SCL
Registers
- Sx Control
Pletronics Inc. certifies this device is in accordance with the
RoHS 6/6 (2002/95/EC) and WEEE (2002/96/EC) directives.
Pletronics Inc. guarantees the device does not contain the following:
Cadmium, Hexavalent Chromium, Lead, Mercury, PBB’s, PBDE’s
Weight of the Device: 0.09 grams
Moisture Sensitivity Level: 1 As defined in J-STD-020C
Second Level Interconnect code: e4
Absolute Maximum Ratings:
Parameter
V
DD
V
DDOUT
Vi
Vo
Io
Input Voltage
Output Voltage
Continuous Output Current
Unit
-0.5V to +2.5V
-0.5V to +4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDOUT
+ 0.5V
_ 50 mA
+
125
o
C
50
o
C/Watt
Tj Maximum Junction Temperature
Thermal Resistance, Junction to Case
Product information is current as of publication date. The product conforms
to specifications per the terms of the Pletronics standard warranty. Production
processsing does not necessarily include testing of all parameters.
Copyright © 2008, Pletronics Inc.
FD5T Series Programmable
CMOS Clock Oscillator
November 2008
Description:
The FD5T series Programmable CMOS Clock Oscillator is a modular PLL-based low cost, high-
performance oscillator. The frequency range is from 12KHz to 230MHZ.
The FD5T base frequency, as noted in the device part number, is established during manufacture and is
permanently fixed. For convenience, the divider for output OUT characteristics may be pre-programmed
at the factory, or field programmed.
The FD5T has a separate output supply pin, V
DDOUT
, for either 1.8, 2.5 or 3.3V output logic levels. The
device supply, V
DD
which provides power to all the internal circuits, is nominally 1.8V.
The deep M/N PLL divider ratio allows the generation of zero-ppm clocks for applications such as WLAN,
BlueTooth, Ethernet, USB, IEEE1394, etc. from the base frequency.
The PLL supports Spread Spectrum Clocking (SSC). SSC may be programmed to be either center-
spread or down-spread. This is an important technique to reduce electro-magnetic interference (EMI).
The device supports non-volatile eePROM programming for easy customization of the device. As
shipped, the device is pre-programmed. Standard combinations are denoted by three characters in the
device part number. However, the FD5T may be reprogrammed to a different configuration.
Reprogramming may be either prior to assembly, or in-circuit via a 2-wire SDA/SCL I
2
C bus. In-circuit
programming is not allowed if the VCXO function is needed.
Two programmable control inputs, S1 and S2, may be used to control various aspects of FD55T operation
including selection of alternative frequency set(s), selection of SSC functionality, output tri-state and
power-down.
Reference Oscillator
The Reference Oscillator is an AT cut quartz crystal based oscillator. This oscillator is very similar to the
Pletronics SM77xxH product oscillator. This signal is the lowest jitter and can be an output or can be
divided down by the Divider #1. The user may specify any frequency between 12MHz and 32MHz for
this reference. All output frequencies are derived from (referenced to) this Reference Oscillator.
The VCXO input has a limited voltage range, the VCXO is associated with the internal 1.8V core. A
resistor in series with the Vcontrol input will permit interfacing to 3.3V analog circuits, the voltage range
that changes the frequency will still be limited but the larger voltages swings will not cause problems.
The VCXO function is only enabled (internally connected) if the part number indicates a VCXO
specification. When the VCXO function is enabled the I
2
C programming mode will be disabled.
PLL Multipliers
The PLL Multiplier can multiply the Reference Oscillator frequency from 1 (bypass mode) to any value
that is <=230MHz (the lowest frequency is the Reference Oscillator frequency).
The PLL Multipliers can have two setup options, 0 or 1, depending on which option is chosen and set by
the Sx control signals and the user’s definitions are stored in eePROM.
Spread Spectrum
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2
FD5T Series Programmable
CMOS Clock Oscillator
November 2008
Each PLL has its individual Spread Spectrum (SS) function that can be enabled. This permits the
modulation of the output frequency by a user-set amount. The modulation can be centered on the
output frequency or down side only. Which of the 1 of 8 SS settings is being used is set by the Sx input
and the user definition. The value is a percentage of the output frequency that will be modulated.
SS Option
0
1
2
3
4
5
6
7
Down Side Modulation
No SS
-0.25%
-0.50%
-0.75%
-1.00%
-1.25%
-1.50%
-2.00%
Centered Modulation
No SS
+0.25%
_
+0.50%
_
+0.75%
_
+1.00%
_
+1.25%
_
+1.50%
_
+2.00%
_
Divider Section
The dividers operate on the output of the PLL. The divider on the PLL can divide by 1 through 127, the
value is user defined. There is only 1 setting allowed per divider. These are not set by the Sx input
state.
The dividers add very little jitter to the output signals.
Multiplexers
MUX #1 selects the input to the Divider #1, this can be the reference oscillator signal or the output from
PLL Multiplier #1. MUX #3 connect various divider outputs to the output buffer.
The device can make only one of the setting of connections shown in the block diagram (only one
pattern stored in eePROM).
Output Buffer
The output buffer can have 3 modes of operation:
1) Tri State
2) Active Low
3) The signal output of the Multiplexer
There can be two options stored for the Output Buffer, State 0 and State 1. The four Sx input settings
can have assigned one of the two Output Buffer states for each of Output Buffer sets.
Control Inputs
The two inputs, S1/SDA and S2/SCL can be configured in two ways.
1) Used as 2 user inputs to permit up to 4 states, Sx input setting.
2) The SDA and SCL become clock and data inputs to write to the FD5T internal setting memory.
The interface follows the I
2
C protocol. If the SDA and SCL are not set then the internal eePROM
sets the operation. (Not allowed if the VCXO function is specified.)
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FD5T Series Programmable
CMOS Clock Oscillator
November 2008
PART NUMBER:
FD5 1 45 T L E -25.0M -YYY -XX
Packaging code or blank
T250 = 250 per Tape and Reel
T500 = 500 per Tape and Reel
T1K = 1000 per Tape and Reel
Configuration Number
This is a 3 character alpha-numeric code issued by
Pletronics that defines the FD5T function (the output pin
functions, the available frequencies and the pin number
assignments). Each configuration is given a unique value.
Base Frequency (Crystal oscillator frequency) in MHZ
Optional Enhanced Operating temperature Range
Blank
= Temp. range -20
o
C to +70
o
C
E
= Temp. range -40
o
C to +85
o
C
Blank
= V
DDOUT
3.3V, 2.5V and 1.8V device
L
= V
DDOUT
1.8V only high output drive level device
Series Model
Frequency Stability for fixed frequency oscillator
45
= + 50 ppm
_
15
= + 15 ppm
_
44
= + 25 ppm
_
10
= + 10 ppm
_
20
= + 20 ppm
_
Frequency Pull Ability for VCXO option enabled
99
= + 100 ppm Absolute Pull Range (APR)
_
75
= _ 25 ppm Absolute Pull Range (APR)
+
50
= _ 50 ppm Absolute Pull Range (APR)
+
1
= 1 output
Series Model
1 PLL version
Part Marking:
PLE FD51
ZZZ
YMD
PLE = Pletronics
ZZZ
= configuration
All other marking is internal factory codes
Marking Legend:
X
YMD
=
=
Model type
Date of Manufacture
(year-month-day)
Codes for Date Code YMD
Code
Code
A
8
9
0
1
2
B
C
D
E
F
G
H
J
K
L
M
Year
2008 2009 2010 2011 2012
Month
JAN FEB MAR APR MAY JUN JUL AUG SEP OCT NOV DEC
Code
Day
Code
Day
1
1
H
17
2
2
J
18
3
3
K
19
4
4
L
20
5
5
M
21
6
6
N
22
7
7
P
23
8
8
R
24
9
9
T
25
A
10
U
26
B
11
V
27
C
12
W
28
D
13
X
29
E
14
Y
30
F
15
Z
31
G
16
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FD5T Series Programmable
CMOS Clock Oscillator
November 2008
Electrical Specification over the specified temperature range
Item
Base Frequency
Frequency Range OUT1
Frequency Range OUT2 - 7
Frequency Accuracy
“45"
“44"
“20"
Recommended Operating Conditions
Device Supply Voltage V
DD
Output Supply Voltage V
DDOUT
Output Supply Voltage “L” V
DDOUT
Low Level Input voltage
High Level Input voltage
Input Voltage Range, S1, S2
Input current for: S1, S2
1.7
1.7
1.7
--
70
0
0
-4
Output Current, V
DDOUT
= 3.3V
Output Current, V
DDOUT
= 2.5V
Output Current, V
DDOUT
= 1.8V
Output Current “L”, V
DDOUT
= 1.8V
Output Load, LVCMOS
-12
-10
-5
-8
--
1.9
3.6
1.9
30
--
3.6
5
0
+12
+10
+5
+8
10
V
V
V
%
%
V
µA
µA
mA
mA
mA
mA
pf
Higher loads can be used
of V
DD
of V
DD
V
TH
is 0.5 * V
DD
V
IN
= V
DD
; V
DD
= 1.9V
V
IN
= 0.0V
D
; V
DD
= 1.9V
Min
12
0.0117
0.0945
-50
-25
-20
Max
32
230
230
+50
+25
+20
Unit
MHZ
MHZ
MHZ
ppm
For all supply voltages, load changes,
aging for 1 year, shock, vibration and
temperatures
Base Frequency / (1 to 1023) -or- PLL1
Condition
LVCMOS Output Parameters for V
DDOUT
= 3.3v
Output High, V
DDOUT
= 3.3V
2.9
2.4
2.2
Output Low, V
DDOUT
= 3.3V
--
--
--
Rise & Fall Time
Output Symmetry
Peak-to-Peak Jitter
(1)(2)
Cycle-to-Cycle Jitter
(1)(2)
--
45
--
--
--
--
--
0.1
0.5
0.8
0.6
55
100
90
V
V
V
V
V
V
nS
%
pS
pS
I
OH
= -0.1 mA
I
OH
= -8.0 mA
I
OH
= -12.0 mA
I
OH
= +0.1 mA
I
OH
= +8.0 mA
I
OH
= +12.0 mA
V
DDOUT
= 3.3v, 20 - 80%, 10pF Load
at 50% point of V
DDOUT
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