Shelf product is a high-performance 1M byte (8Mbit) CMOS
static RAM built with two individual 524,288 x 8 bit SRAMs
with a common output enable. Memory access and control is
provided by an active LOW chip enable (En), an active LOW
output enable (G). This device has a power-down feature that
reduces power consumption by more than 90% when deselected.
Writing to each memory is accomplished by taking one of the
chip enable (En) inputs LOW and write enable (Wn) inputs
LOW. Data on the I/O pins is then written into the location
specified on the address pins (A
0
through A
18
). Reading from
the device is accomplished by taking one ofthe chip enable (En)
and output enable (G) LOW while forcing write enable (Wn)
HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O pins.
Only one SRAM can be read or written at a time.
The input/output pins are placed in a high impedance state when
the device is deselected (En HIGH), the outputs are disabled (G
HIGH), or during a write operation (En LOW and Wn LOW).
E
1
A(18:0)
G
512K x 8
W
1
E
0
W
0
512K x 8
DQ(7:0)
Figure 1. UT8Q1024K8 SRAM Block Diagram
1
DEVICE OPERATION
NC
NC
A0
A1
A2
A3
A4
E1
DQ0
DQ1
V
DD
V
S S
DQ2
DQ3
W1
A5
A6
A7
A8
A9
W2
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
E2
NC
A18
A17
A16
A15
G
DQ7
DQ6
V
SS
V
DD
DQ5
DQ4
A14
A13
A12
A11
A10
NC
NC
NC
Each die in the UT8Q1024K8 has three control inputs called
Enable (En), Write Enable (Wn), and Output Enable (G); 19
address inputs, A(18:0); and eight bidirectional data lines,
DQ(7:0). The device enable (En) controls device selection,
active, and standby modes. Asserting En enables the device,
causes I
DD
to rise to its active value, and decodes the 19 address
inputs to each memory die . Wn controls read and write
operations. During a read cycle, G must be asserted to enable
the outputs.
Table 1. Device Operation Truth Table
G
X
1
X
Wn
X
0
1
1
En
1
0
0
0
I/O Mode
3-state
Data in
3-state
Data out
Mode
Standby
Write
Read
2
Read
Figure 2. 25ns SRAM Pinout (44)
1
0
PIN NAMES
A(18:0)
DQ(7:0)
En
Wn
G
V
DD
V
SS
Address
Data Input/Output
Device Enable
WriteEnable
Output Enable
Power
Ground
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
READ CYCLE
A combination of Wn greater than V
IH
(min) with En and G less
than V
IL
(max) defines a read cycle. Read access time is
measured from the latter of device enable, output enable, or valid
address to valid data output.
SRAM Read Cycle 1, the Address Access is initiated by a change
in address inputs while the chip is enabled with G asserted and
Wn deasserted. Valid data appears on data outputs DQ(7:0) after
the specified t
AVQV
is satisfied. Outputs remain active
throughout the entire cycle. As long as device enable and output
enable are active, the address inputs may change at a rate equal
to the minimum read cycle time (t
AVAV
).
SRAM Read Cycle 2, the Chip Enable-controlled Access is
initiated by En going active while G remains asserted, Wn
remains deasserted, and the addresses remain stable for the
entire cycle. After the specified t
ETQV
is satisfied, the eight-bit
word addressed by A(18:0) is accessed and appears at the data
outputs DQ(7:0).
SRAM Read Cycle 3, the Output Enable-controlled Access is
initiated by G going active while En is asserted, Wn is
deasserted, and the addresses are stable. Read access time is
t
GLQV
unless t
AVQV
or t
ETQV
have not been satisfied.
2
Notes:
1. To avoid bus contention, on the DQ(7:0) bus, only one En can be driven low
simultaneously while G is low.
WRITE CYCLE
A combination of Wn less than V
IL
(max) and En less than
V
IL
(max) defines a write cycle. The state of G is a “don’t care”
for a write cycle. The outputs are placed in the high-impedance
state when eitherG is greater than V
IH
(min), or when Wn is less
than V
IL
(max).
Write Cycle 1, the Write Enable-controlled Access is defined
by a write terminated by Wn going high, with En still active.
The write pulse width is defined by t
WLWH
when the write is
initiated byWn, and by t
ETWH
when the write is initiated by En.
Unless the outputs have been previously placed in the high-
impedance state byG, the user must wait t
WLQZ
before applying
data to the eight bidirectional pins DQ(7:0) to avoid bus
contention.
Write Cycle 2, the Chip Enable-controlled Access is defined by
a write terminated by the former of En or Wn going inactive.
The write pulse width is defined by t
WLEF
when the write is
initiated by Wn, and by t
ETEF
when the write is initiated by the
En going active. For the Wn initiated write, unless the outputs
have been previously placed in the high-impedance state by G,
the user must wait t
WLQZ
before applying data to the eight
bidirectional pins DQ(7:0) to avoid bus contention.
TYPICAL RADIATION HARDNESS
The UT8Q1024K8 SRAM incorporates features which allow
operation in a limited radiation environment.
Table 2. Typical Radiation Hardness
Design Specifications
1
Total Dose
Heavy Ion
Error Rate
2
50
<1E-8
krad(Si) nominal
Errors/Bit-Day
Notes:
1. The SRAM will not latchup during radiation exposure under recommended
operating conditions.
2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of
Aluminum.
3
ABSOLUTE MAXIMUM RATINGS
1
(Referenced to V
SS
)
SYMBOL
V
DD
V
I/O
T
STG
P
D
T
J
Θ
JC
I
I
PARAMETER
DC supply voltage
Voltage on any pin
Storage temperature
Maximum power dissipation
Maximum junction temperature
2
Thermal resistance, junction-to-case
3
DC input current
LIMITS
-0.5 to 4.6V
-0.5 to 4.6V
-65 to +150°C
1.0W (per byte)
+150°C
10°C/W
±
10 mA
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. E xposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175
°C
during burn-in and steady-static life.
3. Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
T
C
V
IN
PARAMETER
Positive supply voltage
Case temperature range
DC input voltage
LIMITS
3.0 to 3.6V
-40 to +125°C
0V to V
DD
4
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
(-40°C to +125°C) (V
DD
= 3.3V + 0.3)
SYMBOL
V
IH
V
IL
V
OL1
V
OL2
V
OH1
V
OH2
C
IN 1
C
IO 1
I
IN
I
OZ
PARAMETER
High-level input voltage
Low-level input voltage
Low-level output voltage
Low-level output voltage
High-level output voltage
High-level output voltage
Input capacitance
Bidirectional I/O capacitance
Input leakage current
Three-state output leakage current
(CMOS)
(CMOS)
I
OL
= 8mA, V
DD
=3.0V
I
OL
= 200µA,V
DD
=3.0V
I
OH
= -4mA,V
DD
=3.0V
I
OH
= -200µA,V
DD
=3.0V
ƒ
= 1MHz @ 0V
ƒ
= 1MHz @ 0V
V
SS
< V
IN
< V
DD,
V
DD
= V
DD
(max)
0V < V
O
< V
DD
V
DD
= V
DD
(max)
G = V
DD
(max)
I
OS2, 3
I
DD
(OP)
Short-circuit output current
Supply current operating
@ 1MHz
0V < V
O
< V
DD
Inputs: V
IL
= 0.8V,
V
IH
= 2.0V
I
OUT
= 0mA
V
DD
= V
DD
(max)
I
DD1
(OP)
Supply current operating
@40MHz
Inputs: V
IL
= 0.8V,
V
IH
= 2.0V
I
OUT
= 0mA
V
DD
= V
DD
(max)
I
DD2
(SB)
Nominal standby supply current
@0MHz
Inputs: V
IL
= V
SS
I
OUT
= 0mA
En = V
DD
- 0.5,
V
DD
= V
DD
(max)
V
IH
= V
DD
- 0.5V
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 101 9 .
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
[i=s]This post was last edited by jishuaihu on 2015-5-11 00:38[/i] I am learning about the four-layer board, and I did not change anything in the schematic. I started to lay out the layout. Here are t...
Compatibility, noise, interference and other issues are inevitable problems in the electronics industry and its products. In PCB samples, magnetic beads are mainly used to solve these problems. Magnet...
The quartus version is 11.1 sp2. When calling the IP core DDR2 SDRAM Controller with uniphy, generation always fails. The specific prompt information is Error: Simulation model generation failed: E:\a...
[size=4] Recently, for some reason, my laptop screen flickers whenever I use the built-in keyboard to type. It happens intermittently[/size]:@:[size=4], I replaced it with an external one and it worke...
My screen is wide. I want to rotate it 90 degrees and use it as a vertical screen. This is the effect1111111111111111111111111 11111111111111111111111 Now it is vertical when I install it. 11 11 11 11...
According to foreign media reports, Ford Motor has applied to the U.S. Patent and Social Security Administration (USPTO) for a patent for a remote vehicle control system that may be used in future ...[Details]
To understand why car engines need gearboxes, we must first understand the characteristics of different types of engines. An engine refers to a machine that can convert a form of energy into kineti...[Details]
Ever since the Tesla fire incident, electric cars, already known for their poor reputation, have been subjected to even more scathing criticism. Despite this, many people are still willing to buy t...[Details]
Limited vocabulary recognition
According to the number of characters, words or short sentences in the vocabulary, it can be roughly divided into: less than 100 is small vocabulary; 100-1000 is...[Details]
White light LEDs are voltage-sensitive devices. In actual operation, their upper limit is 20mA. However, the current often increases due to various reasons during use. If no protective measures are...[Details]
According to foreign media reports, secondary battery materials company POSCO Future M announced that it has successfully developed two experimental (prototype) positive electrode materials for the...[Details]
Robotics
has become
LiDAR
's "second growth curve."
While LiDAR was still battling with its "pure vision" rivals in the automotive field, another field ignited the demand f...[Details]
The Automotive Testing and Quality Assurance Expo (ATE 2025) will open on August 27th. At the expo, Rohde & Schwarz (R&S) will showcase six automotive testing solutions, themed "Intelligently Drivi...[Details]
The all-new MG4 was recently officially announced on the Ministry of Industry and Information Technology's (MIIT) new vehicle announcement. The all-new MG4's semi-solid-state battery version addres...[Details]
This paper proposes a temperature real-time transmission and display solution based on LED optical data transmission, with Jingwei Yager low-power FPGA HR (Yellow River) series as the main controll...[Details]
In the electronics manufacturing industry, surface mount technology (SMT) placement machines are core equipment for production lines. However, with many different models available on the market, ch...[Details]
On August 21st, BYD announced the launch of its next-generation "Little White Pile" product, the "Lingchong"
charging
pile
, which is now available for general sale. This charging pile feat...[Details]
A tubular motor is an electric motor that is typically used to control the movement of machines and equipment. Tubular motors are generally divided into two categories: linear tubular motors and ro...[Details]
A scale, a large, ground-mounted scale, is typically used to measure the tonnage of truck cargo. It's the primary weighing device used in factories, mines, and businesses for bulk cargo measurement...[Details]
As the range of electric vehicles continues to increase, driving electric vehicles for long-distance travel has become a trend. For high-speed travel, how much impact will high-speed driving of ele...[Details]
PCB Design
京公网安备 11010802033920号
EEWORLD
