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UPD44165364F5-E60-EQ1

Description
QDR SRAM, 512KX36, 0.5ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, FBGA-165
Categorystorage    storage   
File Size402KB,32 Pages
ManufacturerNEC Electronics
Download Datasheet Parametric View All

UPD44165364F5-E60-EQ1 Overview

QDR SRAM, 512KX36, 0.5ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, FBGA-165

UPD44165364F5-E60-EQ1 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerNEC Electronics
Parts packaging codeBGA
package instructionBGA,
Contacts165
Reach Compliance Codecompliant
ECCN code3A991.B.2.A
Maximum access time0.5 ns
JESD-30 codeR-PBGA-B165
JESD-609 codee0
length15 mm
memory density18874368 bit
Memory IC TypeQDR SRAM
memory width36
Number of functions1
Number of terminals165
word count524288 words
character code512000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize512KX36
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Package shapeRECTANGULAR
Package formGRID ARRAY
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum supply voltage (Vsup)1.9 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width13 mm
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD44165084, 44165184, 44165364
18M-BIT QDR
TM
II SRAM
4-WORD BURST OPERATION
Description
The
µ
PD44165084 is a 2,097,152-word by 8-bit, the
µ
PD44165184 is a 1,048,576-word by 18-bit and the
µ
PD44165364 is a 524,288-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS
technology using full CMOS six-transistor memory cell.
The
µ
PD44165084,
µ
PD44165184 and
µ
PD44165364 integrates unique synchronous peripheral circuitry and a
burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K and
/K.
These products are suitable for application which require synchronous operation, high speed, low voltage, high
density and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
1.8 ± 0.1 V power supply and HSTL I/O
DLL circuitry for wide output data valid window and future frequency scaling
Separate independent read and write data ports with concurrent transactions
100% bus utilization DDR READ and WRITE operation
Four-tick burst for reduced address frequency
Two input clocks (K and /K) for precise DDR timing at clock rising edges only
Two output clocks (C and /C) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
Internally self-timed write control
Clock-stop capability with
µ
s restart
User programmable impedance output
Fast clock cycle time : 4.0 ns (250 MHz) , 5.0 ns (200 MHz) , 6.0 ns (167 MHz)
Simple control logic for easy depth expansion
JTAG boundary scan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M15825EJ7V1DS00 (7th edition)
Date Published
July
2004 NS CP(K)
Printed in Japan
The mark
shows major revised points.
2001
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