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Bt8953A/SP
HDSL Channel Unit
data sheet
PROVIDING
HIGH
SPEED
MULTIMEDIA
CONNECTIONS
Because
Communication
Matters
™
Advance Information
This document contains information on a product under development. The parametric information contains target
parameters that are subject to change.
Bt8953A/8953SP
HDSL Channel Unit
The Bt8953A is a High-Bit-Rate Digital Subscriber Line (HDSL) channel unit
designed to perform data, clock, and format conversions necessary to construct a
Pulse Code Multiplexed (PCM) channel from one, two, or three HDSL channels.
The PCM channel consists of transmit and receive data, clock and frame sync sig-
nals configured for standard T1 (1544 kbps), standard E1 (2048 kbps), or custom
(Nx64 kbps) formats. The PCM channel connects directly to a Bt8370 T1/E1 Con-
troller or similar T1/E1 device. Connection to other network/subscriber physical
layer devices is supported by the custom PCM frame format. Three identical
HDSL channel interfaces consist of serial data and clock connected to a Bt8970
HDSL Transceiver or similar 2B1Q bit pump device. The Bt8953SP contains one
HDSL channel interface.
Control and status registers are accessed via the Microprocessor Unit (MPU)
interface. One common register group configures the PCM interface formatter,
Pseudo-Random Bit Sequence (PRBS) generator, Bit Error Rate (BER) meter,
timeslot router, Digital Phase Lock Loop (DPLL) clock recovery, and PCM Loop-
backs (LB). Three groups of HDSL channel registers configure the elastic store
FIFOs, overhead muxes, receive framers, payload mappers, and HDSL loopbacks.
Status registers monitor received overhead, DPLL, FIFO, and framer operations,
including CRC and FEBE error counts.
Bt8953A adheres to Bellcore TA-NWT-001210 and FA-NWT-001211, and the
latest ETSI RTR/TM-03036 standards. C-language software for all standard T1/E1
configuration and startup procedures is implemented on Rockwell's HDSL Evalu-
ation Module (Bt8970EVM) and is available under a no-fee license agreement.
Bt8953A software can also be developed for non-standard HDSL applications or
to interoperate with existing HDSL equipment.
Distinguishing Features
•
Supports All HDSL Bit Rates
–
–
–
–
2 pair T1 standard (784 kbps)
2 pair E1 standard (1168 kbps)
3 pair E1 standard (784 kbps)
1/2/3 pair custom (Nx64 kbps)
Connects to Bt8370
Framed or unframed mode
Sync/Async payload mapping
Clock recovery/jitter attenuation
PRBS/fixed test patterns
BER measurement
Connects to Bt8970
Three independent serial channels
Central, remote, or repeater
Overhead (HOH) management
Programmable path delays
Error performance monitoring
Software controlled EOC and IND
Auxiliary payload/Z-bit data link
Master loop ID and interchange
Auto tip/ring reversal
PCM timeslots – HDSL payload
Drop/Insert – HDSL payload
Auxiliary – HDSL payload
PRBS/Fixed – PCM or HDSL
PCM and HDSL loopbacks
•
T1/E1 Primary Rate (PCM) Channel
–
–
–
–
–
–
•
HDSL Channels
–
–
–
–
–
–
–
–
–
–
•
Programmable Data Routing
–
–
–
–
–
Functional Block Diagram
Elastic
Store
Mapper
HOH Mux
2B1Q
Encoder
HDSL
Channels
1, 2, 3
•
•
•
Intel
®
or Motorola
®
MPU interface
CMOS technology, 5 V operation
68-pin PLCC or 80-pin PQFP
PRBS
LB
BER
Timeslot Router
PCM Formatter
Drop
Insert
Applications
•
•
•
•
•
•
•
•
Full, Fractional or Multipoint T1/E1
Single and Multichannel Repeaters
Voice Pair Gain Systems
Wireless LAN/PBX
PCS, Cellular Base Station
Fiber Access/Distribution
Loop Carrier, Remote Switches
Subscriber Line Modem
Stuff
LB
PCM
Channel
Elastic
Store
Payload
Mapper
2B1Q
Decoder
MPU
Registers
DPLL
Receive
Framer
Microprocessor
PLL Filter
Ordering Information
Order Number
Bt8953EPF
(1)
Bt8953AEPJ
(1)
Bt8953AEPFC
Bt8953AEPJC
Bt8953SP EPF
Bt8953SP EPJ
Package
160–Pin Plastic Quad Flat Pack (PQFP)
68–Pin Plastic Leaded Chip Carrier (PLCC)
80–Pin Plastic Quad Flat Pack (PQFP)
68–Pin Plastic Leaded Chip Carrier (PLCC)
80–Pin Plastic Quad Flat Pack (PQFP)
68–Pin Plastic Leaded Chip Carrier (PLCC)
Number of
HDSL Channels
3
3
3
3
1
1
Operating Temperature Range
–40˚C to +85˚C
–40˚C to +85˚C
–40˚C to +85˚C
–40˚C to +85˚C
–40˚C to +85˚C
–40˚C to +85˚C
Notes: (1).Bt8953EPF and Bt8953EPFJ are obsoleted by Bt8953AEPJC. Refer to the Addendum for a description of differences
between Bt8953EPF and Bt8953AEPJ.
Copyright © 1998 Rockwell Semiconductor Systems, Inc. All rights reserved.
Print date: May 1998
Rockwell Semiconductor Systems, Inc. reserves the right to make changes to its products or specifications to improve performance,
reliability, or manufacturability. Information furnished is believed to be accurate and reliable. However, no responsibility is
assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by its implication or otherwise under any patent or intellectual property rights of Rockwell Semiconductor Systems, Inc.
Rockwell Semiconductor Systems, Inc. products are not designed or intended for use in life support appliances, devices, or systems
where malfunction of a Rockwell Semiconductor Systems, Inc. product can reasonably be expected to result in personal injury or
death. Rockwell Semiconductor Systems, Inc. customers using or selling Rockwell Semiconductor Systems, Inc. products for use
in such applications do so at their own risk and agree to fully indemnify Rockwell Semiconductor Systems, Inc. for any damages
resulting from such improper use or sale.
Bt is a registered trademark of Rockwell Semiconductor Systems, Inc. SLC is a registered trademark of AT&T Technologies, Inc.
Product names or services listed in this publication are for identification purposes only, and may be trademarks or registered
trademarks of their respective companies. All other marks mentioned herein are the property of their respective holders.
Specifications are subject to change without notice.
PRINTED IN THE UNITED STATES OF AMERICA
Table of Contents
List of Figures
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
List of Tables
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
1.0 HDSL Systems
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 HTU Applications
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 System Interfaces
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.0 Pin Descriptions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Pin Assignments
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Signal Definitions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.0 Circuit Descriptions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 MPU Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2 PCM Channel
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.1 PCM Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
3.2.2 PCM Receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
3.3 Clock Recovery DPLL
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.4 Loopbacks
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.5 HDSL Channel
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.5.1 HDSL Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
3.5.2 HDSL Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
49
N8953ADSC
iii
Table of Contents
Bt8953A/8953SP
HDSL Channel Unit
4.0 Bt8953 PRA Function
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.1 PRA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.2 Bt8953 Functions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.2.1 Transferring Data from HDSL to RSER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.2 Definitions of Detection Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.3 Inserting Data Transferred from HDSL to RSER . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.4 Transferring Data from TSER to HDSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.5 Inserting Data Transferred from TSER to HDSL . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
56
57
57
58
5.0 Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.1 Address Map
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.2 HDSL Transmit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
0x00—Transmit Embedded Operations Channel (TEOC_LO). . . . . . . . . . . . . . . . . . . . . .
0x01—Transmit Embedded Operations Channel (TEOC_HI) . . . . . . . . . . . . . . . . . . . . . .
0x02—Transmit Indicator Bits (TIND_LO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x03—Transmit Indicator Bits (TIND_HI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x04—Transmit Z-Bits (TZBIT_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x05—Transmit FIFO Water Level (TFIFO_WL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x06—Transmit Command Register 1 (TCMD_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x07—Transmit Command Register 2 (TCMD_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0xDF—Transmit Z-Bits (TZBIT_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0xE0—Transmit Z-Bits (TZBIT_3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0xE1—Transmit Z-Bits (TZBIT_4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0xE2—Transmit Z-Bits (TZBIT_5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0xE3—Transmit Z-Bits (TZBIT_6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
68
68
68
68
69
69
71
72
72
72
72
73
74
74
74
74
75
75
75
75
75
76
76
78
79
80
80
5.3 Transmit Payload Mapper
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
0x08—Transmit Payload Map (TMAP_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x09—Transmit Payload Map (TMAP_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x0A—Transmit Payload Map (TMAP_3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x0B—Transmit Payload Map (TMAP_4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x0C—Transmit Payload Map (TMAP_5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x0F—Transmit Payload Map (TMAP_6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x10—Transmit Payload Map (TMAP_7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x11—Transmit Payload Map (TMAP_8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x12—Transmit Payload Map (TMAP_9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x0D—Transmit FIFO Reset (TFIFO_RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x0E—Scrambler Reset (SCR_RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 HDSL Receive
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
0x60—Receive Command Register 1 (RCMD_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x61—Receive Command Register 2 (RCMD_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x62—Receive Elastic Store FIFO Reset (RFIFO_RST) . . . . . . . . . . . . . . . . . . . . . . . . . .
0x63—Receive Framer Synchronization Reset (SYNC_RST). . . . . . . . . . . . . . . . . . . . . .
iv
N8953ADSC