P
RELIMINARY
P
RODUCT
S
PECIFICATION
1
Z87000/Z87L00
S
PREAD
S
PECTRUM
C
ONTROLLERS
FEATURES
Device
Z87000
Z87L00
ROM
(KWords)
12
12
RAM*
I/O
(Words) Lines
512
512
32
32
Package
Information
84-Pin PLCC
100-Pin QFP
100-Pin QFP
s
1
Transceiver Circuitry Provides Primary Cordless Phone
Communications Functions
– Digital Downconversion with Automatic Frequency
Control (AFC) Loop
– FSK Demodulator
–
–
–
FSK Modulator
Symbol Synchronizer
Time Division Duplex (TDD) Transmit and Receive
Buffers
Note:
*General-Purpose
s
Transceiver/Controller Chip Optimized for Implement-
ation of 900 MHz Spread Spectrum Cordless Phone
– Adaptive Frequency Hopping
– Transmit Power Control
– Error Control Signaling
– Handset Power Management
– Support of 32 kbps ADPCM Speech Coding for
High Voice Quality
DSP Core Acts as Phone Controller
– Zilog-Provided Embedded Transceiver Software to
Control Transceiver Operation and Base Station-
Handset Communications Protocol
– User-Modifiable Software Governs Phone
Features
s
s
s
s
On-Chip A/D and D/A to Support 10.7 MHz IF Interface
Bus Interface to Z87010 ADPCM Processor
Static CMOS for Low Power Consumption
3.0V to 3.6V, -20
°
C to +70
°
C, Z87L00
4.5V to 5.5V, -20
°
C to +70
°
C, Z87000
16.384 MHz Base Clock
s
s
GENERAL DESCRIPTION
The Z87000/Z87L00 FHSS Cordless Telephone Trans-
ceiver/Controllers are expressly designed to implement a
900 MHz frequency hopping spread spectrum cordless
telephone compliant with United States FCC regulations
for unlicensed operation. The Z87000 and Z87L00 are dis-
tinct 5V and 3.3V versions, respectively, of the device. For
the sake of brevity, all subsequent references to the
Z87000 in this document also apply to the Z87L00, unless
specifically noted.
The Z87000 supports a specific cordless phone system
design that uses frequency hopping and digital modulation
to provide extended range, high voice quality, and low sys-
tem costs.The Z87000 uses a Zilog 16-bit fixed-point two’s
complement static CMOS Digital Signal Processor core as
the phone and RF section controller. The Z87000’s DSP
core processor further supports control of the RF section’s
frequency synthesizer for frequency hopping and the gen-
eration of the control messages needed to coordinate in-
corporation of the phone’s handset and base station.
DS96WRL0501
PRELIMINARY
1-1
Z87000/Z87L00
Spread Spectrum Controllers
Zilog
GENERAL DESCRIPTION
(Continued)
Additional on-chip transceiver circuitry supports Frequen-
cy Shift Keying modulation/demodulation and multiplex-
ing/demultiplexing of the 32 kbps voice data and 4 kbps
command data between handset and base station. The
Z87000 provides thirty-two I/O pins, including four wake-
up inputs and two CPU interrupt inputs. These program-
mable I/O pins allow a variety of user-determined phone
features and board layout configurations. Additionally, the
pins may be used so that phone features and interfaces
are supported by an optional microcontroller rather than by
the Z87000’s DSP core.
In combination with an RF section designed according to
the system specifications, Zilog’s Z87010/Z87L10 ADPCM
Processor, a standard 8-bit PCM telephone CODEC and
minimal additional phone circuity, the Z87000 and its em-
bedded software provide a total system solution.
CODEC
CODEC
Z87010
ADPCM
Processor
Z87000
Spread
Spectrum
Controller
RF Section
RF Section
Z87000
Spread
Spectrum
Controller
Z87010
ADPCM
Processor
Telephone
Line
Interface
Base Station
Handset
Figure 1. System Block Diagram of a Z87000/Z87010 Based Phone
1-2
PRELIMINARY
DS96WRL0501
Zilog
Z87000/Z87L00
Spread Spectrum Controllers
RX
VREF
ADC
(1-bit)
FSK Demodulator
(downconverter, limiter discriminator,
AFC, bit sync, frame sync, SNR
detector)
Receive
Rate
Buffer
Z87010
Interface
VXDATA[7..0]
VXADD[2..0]
VXSTRB
VXRWB
VXRDYB
CLKOUT
CODCLK
1
TX
DAC
(4-bit)
FSK Modulator
Transmit
Rate
Buffer
RXON
RFRX
RFTX
RFEON
SYLE
Frame Counter(s),
Event Trigger,
T/R Switch Ctrl,
Power On/Off Ctrl,
Antenna Select
256 Word
RAM 0
256 Word
RAM 1
Port 0
P0[15..0]
RSSI
ADC
(8-bit)
DAC
(4-bit)
DSP Core
PWLV
ANT0
ANT1
HBSW
RESETB
TEST
12K Words
Program ROM
Port 1
P1[15..0]
Analog
Power
Digital
Power
AVDD
AGND
VDD
GND
Figure 2. Z87000 Functional Block Diagram
DS96WRL0501
PRELIMINARY
1-3
Z87000/Z87L00
Spread Spectrum Controllers
Zilog
PIN DESCRIPTION
AVDD
RSSI
PWLV
AGND
RFRX
RXON
SYLE
RFTX
VDD
MCLK
GND
/RESETB
CODCLK
VXADD0
VXADD1
VXADD2
VDD
VXRWB
VXSTRB
VXRDYB
GND
TX
AGND
RX
AVDD
VREF
RFEON
P115
GND
P114
P113
P112
VDD
P111
P110
P19
GND
P18
P17
P16
VDD
P15
12
1
75
Z87000
33
54
VXDATA0
VXDATA1
VXDATA2
VDD
VXDATA3
VXDATA4
VXDATA5
VXDATA6
VXDATA7
CLKOUT
HBSW
GND
TEST
VDD
ANT0
ANT1
P00
P01
GND
P02
P03
Figure 3. 84-Pin PLCC ROM Pin Configuration (Z87000 only)
1-4
P14
P13
P12
GND
P11
P10
P015
P014
VDD
P013
P012
P011
P010
GND
P09
P08
P07
P06
VDD
P05
P04
PRELIMINARY
DS96WRL0501
Zilog
Table 1. 84-Pin PLCC Pin Description Summary
Pin Number
1,19,27,36,46,
56,63,75
2
3,23,31,41,51,
61,71,79
4
5
6
7
8,13
9
10
11,15
12
14
16
17
18,20,21,22,24,
25,26,28,29,30,
32,33,34,35,37,38
59,60
62
64
65
76
77
78
80,81,82
83
84
GND
MCLK
V
DD
RFTX
SYLE
RXON
RFRX
AGND
PWLV
RSSI
AV
DD
TX
RX
V
REF
RFEON
P115
Symbol
Ground
Master clock (16.384 MHz)
Digital
RF transmit switch control
RF synthesizer load enable
Demodulator “on” indication
RF receive switch control
Analog ground
RF transmit power level
RF receive signals strength indicator
Analog V
DD
Analog transmit IF signal
Analog receive IF signal
Analog reference voltage for RX signal
RF module on/off control
General-purpose
Function
Z87000/Z87L00
Spread Spectrum Controllers
Direction
–
Input
–
Output
Output
Output
Output
–
Output
Input
–
Output
Input
Output
Output
Input
1
ANT1
TEST
HBSW
CLKOUT
VXRDYB
VXSTRB
VXRWB
VXADD2
CODCLK
/RESETB
RF diversity antenna control
Main test mode control
Handset/Base Control
Clock output to ADPCM Processor
ADPCM processor ready signal
ADPCM processor data strobe
ADPCM read/write control
ADPCM processor address bus
Clock output to codec
Reset signal
Input/Output
Input
–
Output
Output
Input
Input
Input
Output
Input
DS96WRL0501
PRELIMINARY
1-5