Data Sheet
FEATURES
Full 16-bit performance
3 V and 5 V single-supply operation
Low 0.625 mW power dissipation
1 µs settling time
Unbuffered voltage output capable of driving 60 kΩ
loads directly
SPI-/QSPI-/MICROWIRE-compatible interface standards
Power-on reset clears DAC output to 0 V (unipolar mode)
5 kV HBM ESD classification
Low glitch: 1.1 nV-sec
2.7 V to 5.5 V, Serial-Input,
Voltage-Output, 16-Bit DACs
AD5541/AD5542
FUNCTIONAL BLOCK DIAGRAMS
V
DD
8
AD5541
REF
3
16-BIT DAC
1
2
V
OUT
AGND
CS
4
DIN
6
16-BIT DAC LATCH
CONTROL
LOGIC
SERIAL INPUT REGISITER
7
07557-001
SCLK
5
DGND
Figure 1. AD5541
APPLICATIONS
Digital gain and offset adjustment
Automatic test equipment
Data acquisition systems
Industrial process control
AD5542
R
INV
REFF
6
V
DD
14
R
FB
1
13
RFB
INV
V
OUT
AGNDF
16-BIT DAC
REFS
5
CS
7
LDAC
11
SCLK
8
DIN
10
CONTROL
LOGIC
SERIAL INPUT REGISITER
12
2
3
GENERAL DESCRIPTION
The AD5541/AD5542 are single, 16-bit, serial input, voltage
output digital-to-analog converters (DACs) that operate from
a single 2.7 V to 5.5 V supply. The DAC output range extends
from 0 V to V
REF
.
The DAC output range extends from 0 V to V
REF
and is guaranteed
monotonic, providing 1 LSB INL accuracy at 16 bits without
adjustment over the full specified temperature range of −40°C to
+85°C. Offering unbuffered outputs, the AD5541/AD5542
achieve a 1 µs settling time with low power consumption and low
offset errors. Providing a low noise performance of 11.8 nV/√Hz
and low glitch, the AD5541/AD5542 is suitable for deployment
across multiple end systems.
The AD5542 can be operated in bipolar mode, which generates
a ±V
REF
output swing. The AD5542 also includes Kelvin sense
connections for the reference and analog ground pins to reduce
layout sensitivity.
The AD5541/AD5542 utilize a versatile 3-wire interface that is
compatible with SPI, QSPI™, MICROWIRE™ and DSP interface
standards. The AD5541/AD5542 are available in 8-lead and
14-lead SOIC packages.
16-BIT DAC LATCH
4
AGNDS
DGND
Figure 2. AD5542
Table 1.
Part No.
AD5541A/AD5542A
AD5024/AD5044/AD5064
AD5062
AD5063
Description
Single, 16-bit unbuffered
nanoDAC™,
±1 LSB INL, LFCSP
Quad 12-/14-/16-bit
nanoDAC,
±1 LSB INL, TSSOP
Single, 16-bit
nanoDAC,
±1 LSB INL,
SOT-23
Single, 16-bit
nanoDAC,
±1 LSB INL,
SOT-23
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
Single-Supply Operation. The AD5541 and AD5542 are fully
specified and guaranteed for a single 2.7 V to 5.5 V supply.
Low Power Consumption. These parts consume typically
0.625 mW with a 5 V supply and 0.375 mV at 3 V.
3-Wire Serial Interface.
Unbuffered Output Capable of Driving 60 kΩ Loads. This
reduces power consumption because there is no internal
buffer to drive.
Power-On Reset Circuitry.
5.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©1999–2012 Analog Devices, Inc. All rights reserved.
07557-002
AD5541/AD5542
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 4
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Terminology .................................................................................... 10
Theory of Operation ...................................................................... 11
Digital-to-Analog Section ......................................................... 11
Serial Interface ............................................................................ 11
Unipolar Output Operation ...................................................... 11
Data Sheet
Bipolar Output Operation ......................................................... 12
Output Amplifier Selection ....................................................... 12
Force Sense Amplifier Selection ............................................... 12
Reference and Ground ............................................................... 12
Power-On Reset .......................................................................... 13
Power Supply and Reference Bypassing .................................. 13
Microprocessor Interfacing ........................................................... 14
AD5541/AD5542 to ADSP-21xx Interface ............................. 14
AD5541/AD5542 to 68HC11/68L11 Interface....................... 14
AD5541/AD5542 to MICROWIRE Interface ........................ 14
AD5541/AD5542 to 80C51/80L51 Interface .......................... 14
Applications Information .............................................................. 15
Optocoupler Interface ................................................................ 15
Decoding Multiple AD5541/AD5542s .................................... 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 17
REVISION HISTORY
3/12—Rev. E to Rev. F
Change to Figure 19 ......................................................................... 9
Changes to Ordering Guide .......................................................... 17
3/11—Rev. D to Rev. E
Changed +105°C to +85°C, General Description Section .......... 1
2/11—Rev. C to Rev. D
Changes to Features Section, General Description Section,
Product Highlights Section ............................................................. 1
Added Table 1; Renumbered Sequentially .................................... 1
Added Output Noise Spectral Density Parameter and Output
Noise Parameter, Table 2.................................................................. 3
Changes to Ordering Guide .......................................................... 17
4/10—Rev. B to Rev. C
Changes to General Description Section ...................................... 1
Changes to Features List .................................................................. 1
Changes to Product Highlights .......................................................1
Changes to Table 1.............................................................................3
Changes to Table 3.............................................................................5
Changes to Figure 16, Figure 17, and Figure 19 ....................... 8, 9
Changes to Theory of Operations Section .................................. 11
Changes to Microprocessor Interfacing Section ........................ 14
Changes to Outline Dimensions .................................................. 16
Changes to Ordering Guide .......................................................... 17
8/08—Rev. A to Rev. B
Updated Format .................................................................. Universal
Changes to Timing Characteristics Section ...................................4
Changes to Table 3.............................................................................5
Updated Outline Dimensions ....................................................... 16
Changes to Ordering Guide .......................................................... 17
10/99—Rev. 0 to Rev. A
Rev. F | Page 2 of 20
Data Sheet
SPECIFICATIONS
AD5541/AD5542
V
DD
= 2.7 V to 5.5 V, 2.5 V ≤ V
REF
≤ V
DD
, AGND = DGND = 0 V. All specifications T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
1
STATIC PERFORMANCE
Resolution
Relative Accuracy (INL)
Min
16
±0.5
±0.5
±0.5
±0.5
+0.5
±0.1
±0.3
±0.05
1.000
±0.0015
±1
±0.2
±1
+1
±0.1
0
−V
REF
1
17
1.1
0.2
6.25
11.8
0.134
±1.0
2.0
9
7.5
V
DD
V
REF
− 1 LSB
V
REF
− 1 LSB
±1.0
±2.0
±4.0
±1.0
±1.5
±2
±3
±0.7
±1.5
Typ
Max
Unit
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
ppm/°C
LSB
LSB
ppm/°C
Ω/Ω
%
LSB
LSB
ppm/°C
LSB
LSB
LSB
LSB
ppm/°C
V
V
μs
V/μs
nV-sec
nV-sec
kΩ
nV/√Hz
µV p-p
LSB
V
kΩ
kΩ
μA
V
V
pF
V
MHz
mV p-p
dB
pF
pF
Rev. F | Page 3 of 20
Test Conditions
Differential Nonlinearity (DNL)
Gain Error
Gain Error Temperature Coefficient
Unipolar Zero Code Error
Unipolar Zero Code Temperature Coefficient
AD5542
Bipolar Resistor Matching
Bipolar Zero Offset Error
Bipolar Zero Temperature Coefficient
Bipolar Zero Code Offset Error
Bipolar Gain Error
Bipolar Gain Temperature Coefficient
OUTPUT CHARACTERISTICS
Output Voltage Range
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
DAC Output Impedance
Output Noise Spectral Density
Output Noise
Power Supply Rejection Ratio
DAC REFERENCE INPUT
Reference Input Range
Reference Input Resistance
2
LOGIC INPUTS
Input Current
Input Low Voltage, V
INL
Input High Voltage, V
INH
Input Capacitance
3
Hysteresis Voltage
3
REFERENCE
3
Reference −3 dB Bandwidth
Reference Feedthrough
Signal-to-Noise Ratio
Reference Input Capacitance
L, C grades
B, J grades
A grade
Guaranteed monotonic
J grade
T
A
= 25°C
T
A
= 25°C
±0.0076
±5
±6
±5
R
FB
/R
INV
, typically R
FB
= R
INV
= 28 kΩ
Ratio error
T
A
= 25°C
T
A
= 25°C
T
A
= 25°C
±6
±5
±6
Unipolar operation
AD5542 bipolar operation
To 1/2 LSB of FS, C
L
= 10 pF
C
L
= 10 pF, measured from 0% to 63%
1 LSB change around the major carry
All 1s loaded to DAC, V
REF
= 2.5 V
Tolerance typically 20%
DAC code = 0x8400, frequency = 1 kHz
0.1 Hz to 10 Hz
ΔV
DD
± 10%
Unipolar operation
AD5542, bipolar operation
±1
0.8
2.4
10
0.15
2.2
1
92
26
26
All 1s loaded
All 0s loaded, V
REF
= 1 V p-p at 100 kHz
Code 0x0000
Code 0xFFFF
AD5541/AD5542
Parameter
1
POWER REQUIREMENTS
V
DD
I
DD
Power Dissipation
1
2
Data Sheet
Min
2.7
125
0.625
Typ
Max
5.5
150
0.825
Unit
V
μA
mW
Test Conditions
Digital inputs at rails
Temperature ranges are as follows: A, B, C versions: −40°C to +85°C; J, L versions: 0°C to 70°C.
Reference input resistance is code-dependent, minimum at 0x8555.
3
Guaranteed by design, not subject to production test.
TIMING CHARACTERISTICS
V
DD
= 2.7 V to 5.5 V ±10%, V
REF
= 2.5 V, V
INH
= 3 V and 90% of V
DD
, V
INL
= 0 V and 10% of V
DD
, AGND = DGND = 0 V; −40°C < T
A
<
+85°C, unless otherwise noted.
Table 3.
Parameter
1, 2
f
SCLK
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
9
t
10
t
11
t
12
1
2
Limit
25
40
20
20
10
15
30
20
15
4
7.5
30
30
30
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Description
SCLK cycle frequency
SCLK cycle time
SCLK high time
SCLK low time
CS low to SCLK high setup
CS high to SCLK high setup
SCLK high to CS low hold time
SCLK high to CS high hold time
Data setup time
Data hold time (V
INH
= 90% of V
DD
, V
INL
= 10% of V
DD
)
Data hold time (V
INH
= 3V, V
INL
= 0 V)
LDAC pulse width
CS high to LDAC low setup
CS high time between active periods
Guaranteed by design and characterization. Not production tested
All input signals are specified with t
R
= t
F
= 1 ns/V and timed from a voltage level of (V
INL
+ V
INH
)/2.
t
1
SCLK
t
6
t
4
CS
t
2
t
3
t
7
t
5
t
12
t
8
t
5
DIN
DB15
t
11
LDAC*
*AD5542 ONLY. CAN BE TIED PERMANENTLY LOW IF REQUIRED.
07557-003
t
10
Figure 3. Timing Diagram
Rev. F | Page 4 of 20
Data Sheet
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted.
Table 4.
Parameter
V
DD
to AGND
Digital Input Voltage to DGND
V
OUT
to AGND
AGND, AGNDF, AGNDS to DGND
Input Current to Any Pin Except Supplies
Operating Temperature Range
Industrial (A, B, C Versions)
Commercial (J, L Versions)
Storage Temperature Range
Maximum Junction Temperature (T
J
max)
Package Power Dissipation
Thermal Impedance, θ
JA
SOIC (R-8)
SOIC (R-14)
Lead Temperature, Soldering
Peak Temperature
1
ESD
2
1
2
AD5541/AD5542
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
−0.3 V to +6 V
−0.3 V to V
DD
+ 0.3 V
−0.3 V to V
DD
+ 0.3 V
−0.3 V to +0.3 V
±10 mA
−40°C to +85°C
0°C to 70°C
−65°C to +150°C
150°C
(T
J
max – T
A
)/θ
JA
149.5°C/W
104.5°C/W
260°C
5 kV
ESD CAUTION
As per JEDEC Standard 20.
HBM Classification
.
Rev. F | Page 5 of 20
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