DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD77016
16 bits, Fixed-point Digital Signal Processor
µ
PD77016 is a 16 bits fixed-point DSP (Digital Signal Processor) developed for digital signal processing with its
demand for high speed and precision.
FEATURES
•
FUNCTIONS
• Instruction cycle: 30 ns (MIN.) with 33 MHz clock
• Dual load/store
• Hardware loop function
• Conditional execution
• Executes product-sum operation in one instruction cycle
•
PROGRAMMING
• 16 bits
×
16 bits + 40 bits
→
40 bits multiply accumulator
• 8 general registers (40 bits each)
• 8 ROM/RAM data pointer: each data memory area has 4 registers
• 10 source interrupts (external: 4, internal: 6)
• 3 operand instructions (example: R0 = R0 +R1L∗R2L)
• Nonpipeline on execution stage
•
MEMORY AREAS
• Program memory area: 64K words
×
32 bits
• Two independent data memory areas: 64K words
×
16 bits (X/Y memory)
•
ON-CHIP PERIPHERAL
• I/O port: 4 bits
• Serial I/O (16 bits): 2 channels
•
CMOS
•
+5 V single power supply
ORDERING INFORMATION
Part Number
Package
µ
PD77016GM-KMD 160-pin plastic QFP (FINE PITCH) (24
×
24 mm)
The information in this document is subject to change without notice.
Document No. U10891EJ5V0DS00 (5th edition)
Date Published April 1998 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1992, 1994, 1995
4
µ
PD77015
µ
PD77017
µ
PD77018
µ
PD77018A
µ
PD77019
4K words
24K words
None
1K words each
2K words each
16K words each
30 ns (33 MHz)
16.6 ns (60 MHz)
4K words each
12K words each
2K words each
3K words each
None
None
256 words
4K words
12K words
Functional Differences among the
µ
PD7701× Family
µ
PD77019-013
Item
µ
PD77016
Internal instruction RAM
1.5K words
Internal instruction ROM
None
External instruction memory
48K words
Data RAM (X/Y memory)
2K words each
Data ROM (X/Y memory)
None
External data memory
48K words each
Instruction cycle
(Maximum operation speed)
External clock
(at maximum operation speed)
33/16.5/8.25/4.125 MHz
Variable multiple rate (1, 2, 4, 8 ) by mask option.
66 MHz
60/30/20/15/7.5 MHz
Variable multiple rate (1, 2, 3, 4, 8 ) by
mask option.
60 MHz
15 MHz
Multiple rate is
fixed to 4.
–
Crystal
(at maximum operation speed)
33 MHz
–
Instruction
–
STOP instruction is added.
Channel 1 has the same functions as that of the
µ
PD77016.
Channel 2 has no SORQ2 or SIAK2 pin (Channel 2 is used for CODEC connection).
3V
100-pin plastic TQFP
100-pin plastic TQFP
116-pin plastic BGA
100-pin plastic TQFP
Serial interface (2 Channels)
Channel 1 has the
same functions
as channel 2.
Power supply
5V
Package
160-pin plastic QFP
Remark
The
µ
PD77019-013 internal ROM area is masked already by the void code to use as RAM based DSP without mask code ordering process.
µ
PD77016
µ
PD77016
PIN CONFIGURATION
µ
PD77016GM-KMD
160-pin plastic QFP (FINE PITCH) (24
×
24 mm) (Top View)
160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
RESET
INT4
INT3
INT2
INT1
WAIT
HOLDRQ
CLKIN
P3
P2
P1
P0
CLKOUT
GND
V
DD
MWR
MRD
BSTB
HOLDAK
X/Y
DA15
DA14
DA13
DA12
GND
V
DD
DA11
DA10
DA9
DA8
DA7
DA6
DA5
DA4
GND
V
DD
DA3
DA2
DA1
DA0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
IA0
IA1
IA2
IA3
V
DD
GND
IA4
IA5
IA6
IA7
IA8
IA9
IA10
IA11
V
DD
GND
IA12
IA13
IA14
IA15
TMS
TDI
TCK
TIC
TDO
V
DD
GND
HWE
HRE
HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
HA1
HA0
HWR
D15
D14
D13
D12
GND
V
DD
D11
D10
D9
D8
D7
D6
D5
D4
GND
V
DD
D3
D2
D1
D0
GND
V
DD
SI1
SIEN1
SCK1
SIAK1
SO1
SORQ1
SOEN1
GND
V
DD
SOEN2
SORQ2
SO2
SIAK2
SCK2
SIEN2
SI2
HCS
HRD
NC
ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
V
DD
GND
ID8
ID9
ID10
ID11
ID12
ID13
ID14
ID15
V
DD
GND
ID16
ID17
ID18
ID19
ID20
ID21
ID22
ID23
V
DD
GND
PWR
ID24
ID25
ID26
ID27
ID28
ID29
ID30
ID31
5
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