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V53C8258HP35

Description
EDO DRAM, 256KX8, 35ns, CMOS, PDIP24, 0.300 INCH, PLASTIC, DIP-24
Categorystorage    storage   
File Size217KB,18 Pages
ManufacturerMosel Vitelic Corporation ( MVC )
Websitehttp://www.moselvitelic.com
Download Datasheet Parametric View All

V53C8258HP35 Overview

EDO DRAM, 256KX8, 35ns, CMOS, PDIP24, 0.300 INCH, PLASTIC, DIP-24

V53C8258HP35 Parametric

Parameter NameAttribute value
MakerMosel Vitelic Corporation ( MVC )
Parts packaging codeDIP
package instructionDIP, DIP24,.3
Contacts24
Reach Compliance Codeunknown
ECCN codeEAR99
access modeFAST PAGE WITH EDO
Maximum access time35 ns
Other featuresRAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH
I/O typeCOMMON
JESD-30 codeR-PDIP-T24
memory density2097152 bit
Memory IC TypeEDO DRAM
memory width8
Number of functions1
Number of ports1
Number of terminals24
word count262144 words
character code256000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize256KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP24,.3
Package shapeRECTANGULAR
Package formIN-LINE
power supply5 V
Certification statusNot Qualified
refresh cycle512
Maximum seat height4.572 mm
Maximum standby current0.001 A
Maximum slew rate0.16 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
width7.62 mm

V53C8258HP35 Preview

MOSEL VITELIC
V53C8258H
HIGH PERFORMANCE
256K X 8 EDO PAGE MODE
CMOS DYNAMIC RAM
V53C8258H
PRELIMINARY
HIGH PERFORMANCE
Max.
RAS
Access Time, (t
RAC
)
Max. Column Address Access Time, (t
CAA
)
Min. Extended Data Out Page Mode Cycle Time, (t
PC
)
Min. Read/Write Cycle Time, (t
RC
)
35
35 ns
18 ns
14 ns
70 ns
40
40 ns
20 ns
15 ns
75 ns
45
45 ns
22 ns
17 ns
80 ns
50
50 ns
24 ns
19 ns
90 ns
Features
s
256K x 8-bit organization
s
EDO Page Mode for a sustained data rate
of 71 MHz
s
RAS
access time: 35, 40, 45, 50 ns
s
Low power dissipation
s
Read-Modify-Write,
RAS-Only
Refresh,
CAS-Before-RAS
Refresh capability
s
Refresh Interval: 512 cycles/8 ms
s
Available in 24 pin 300 mil Plastic DIP,
26/24 pin 300 mil SOJ and 28-pin 300 mil
TSOP-I packages
s
Single 5V±10% Power Supply
s
TTL Interface
Description
The V53C8258H is a high speed 262,144 x 8 bit
CMOS dynamic random access memory.
The V53C8258H offers a combination of features:
Page Mode with Extended Data Output for high
data bandwidth, and Low CMOS standby current.
All inputs and outputs are TTL compatible. Input
and output capacitances are significantly lowered to
allow increased system performance. Page Mode
with Extended Data Output operation allows
random access of up to 512 (x8) bits within a row
with cycle times as fast as 14 ns. Because of static
circuitry, the
CAS
clock is not in the critical timing
path. The flow-through column address latches
allow address pipelining while relaxing many critical
system timing requirements. The V53C8258H is
ideally suited for graphics, digital signal processing
and high-performance computing systems.
Device Usage Chart
Operating
Temperature
Range
0°C to 70
°C
Package Outline
P
K
T
35
Access Time (ns)
40
45
50
Power
Std.
Temperature
Mark
Blank
1
V53C8258H Rev. 1.4 February 1997
MOSEL VITELIC
V
5
3
C
8
2
5
8
H
V53C8258H
FAMILY
DEVICE
P (PLASTIC DIP)
K (SOJ)
T (TSOP-I)
PKG
Description
Plastic DIP
SOJ
TSOP-I
Pkg.
P
K
T
Pin Count
24
26/24
28
SPEED
( t
RAC
)
TEMP.
PWR.
BLANK (0°C to 70°C)
BLANK (NORMAL)
35ns
40ns
45ns
50ns
8258H-01
26/24 Lead SOJ
PIN CONFIGURATION
Top View
V
SS
I/O
1
I/O
2
I/O
3
I/O
4
WE
RAS
A
0
A
1
A
2
A
3
V
CC
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
16
16
15
14
V
SS
I/O
8
I/O
7
I/O
6
I/O
5
CAS
OE
A
8
A
7
A
6
A
5
A
4
24 Lead Plastic DIP
PIN CONFIGURATION
Top View
V
SS
I/O
1
I/O
2
I/O
3
I/O
4
WE
RAS
A
0
A
1
A
2
A
3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
SS
I/O
8
I/O
7
I/O
6
I/O
5
CAS
OE
A
8
A
7
A
6
A
5
A
4
300 mil
8258H-02
28 Lead TSOP-I
PIN CONFIGURATION
Top View
CAS
I/O5
I/O6
I/O7
I/O8
VSS
VSS
NC
I/O1
I/O2
I/O3
I/O4
NC
WE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
8258H-04
Pin Names
A
0
–A
8
RAS
OE
A8
A7
A6
A5
A4
NC
VCC
NC
A3
A2
A1
A0
RAS
Address Inputs
Row Address Strobe
Column Address Strobe
Write Enable
Output Enable
Data Input, Output
+5V Supply
0V Supply
No Connect
CAS
WE
OE
I/O
1
–I/O
8
V
CC
V
SS
NC
Absolute Maximum Ratings*
Ambient Temperature
Under Bias ............................. –10°C to +80°C
Storage Temperature (plastic) ... –55°C to +125°C
Voltage Relative to V
SS ....................
–1.0 V to +7.0 V
Data Output Current .................................... 50 mA
Power Dissipation ........................................ 1.0 W
*Note: Operation above Absolute Maximum Ratings can
adversely affect device reliability.
Capacitance*
T
A
= 25°C, V
CC
= 5 V
±
10%, V
SS
= 0 V
Symbol
C
IN1
C
IN2
C
OUT
Parameter
Address Input
RAS, CAS, OE, WE
Data Input/Output
Typ. Max.
3
4
5
4
5
7
Unit
pF
pF
pF
* Note: Capacitance is sampled and not 100% tested
V53C8258H Rev. 1.4 February 1997
2
300 mil
8258H-03
MOSEL VITELIC
Block Diagram
256K x 8
OE
WE
CAS
RAS
V53C8258H
RAS CLOCK
GENERATOR
CAS CLOCK
GENERATOR
WE CLOCK
GENERATOR
OE CLOCK
GENERATOR
VCC
VSS
DATA I/O BUS
COLUMN DECODERS
Y0–Y8
I/O 1
I/O2
I/O3
I/O
BUFFER
I/O4
I/O 5
I/O6
I/O7
I/O8
SENSE AMPLIFIERS
REFRESH
COUNTER
512 x 8
9
A0
A1
A7
A8
ADDRESS BUFFERS
AND PREDECODERS
X0–X8
ROW
DECODERS
512
MEMORY
ARRAY
8258H-05
V53C8258H Rev. 1.4 February 1997
3
MOSEL VITELIC
DC and Operating Characteristics
(1-2)
T
A
= 0°C to 70°C, V
CC
= 5 V
±
10%, V
SS
= 0 V, unless otherwise specified.
Symbol
Parameter
V53C8258H
Access
Time Min. Typ. Max..
–10
10
V53C8258H
Unit
µA
Test Conditions
V
SS
V
IN
V
CC
Notes
I
LI
Input Leakage Current
(any input pin)
Output Leakage Current
(for High-Z State)
35
I
LO
–10
10
µA
V
SS
V
OUT
V
CC
RAS, CAS
at V
IH
160
150
145
135
RAS, CAS
at V
IH
other inputs
V
SS
mA
t
RC
= t
RC
(min.)
1, 2
I
CC1
V
CC
Supply Current,
Operating
40
45
50
I
CC2
V
CC
Supply Current,
TTL Standby
V
CC
Supply Current,
RAS-Only
Refresh
35
40
45
50
2
160
150
145
135
95
90
85
80
2.0
mA
I
CC3
mA
t
RC
= t
RC
(min.)
2
I
CC4
V
CC
Supply Current,
EDO Page Mode
Operation
35
40
45
50
mA
Minimum cycle
1, 2
I
CC5
V
CC
Supply Current,
Standby, Output Enabled
V
CC
Supply Current,
CMOS Standby
mA
RAS=V
IH
,
CAS=V
IL
other inputs
V
SS
RAS
V
CC
– 0.2 V,
CAS
V
CC
– 0.2 V,
All other inputs
V
SS
1
I
CC6
1.0
mA
V
IL
V
IH
V
OL
V
OH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–1
2.0
0.8
V
CC
+1
0.4
V
V
V
V
I
OL
= 4.2 mA
I
OH
= –5 mA
3
3
2.4
V53C8258H Rev. 1.4 February 1997
4
MOSEL VITELIC
AC Characteristics
T
A
= 0°C to 70°C, V
CC
= 5 V
±10%,
V
SS
= 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
JEDEC
Symbol
t
RL1RH1
t
RL2RL2
t
RH2RL2
t
RL1CH1
t
CL1CH1
t
RL1CL1
t
WH2CL2
t
AVRL2
t
RL1AX
t
AVCL2
t
CL1AX
35
Symbol
t
RAS
t
RC
t
RP
t
CSH
t
CAS
t
RCD
t
RCS
t
ASR
t
RAH
t
ASC
t
CAH
Parameter
RAS
Pulse Width
Read or Write Cycle Time
RAS
Precharge Time
CAS
Hold Time
CAS
Pulse Width
RAS
to
CAS
Delay
Read Command Setup Time
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
Column Address Hold Time
RAS
Hold Time (Read Cycle)
CAS
to
RAS
Precharge Time
Read Command Hold Time
Referenced to
CAS
Read Command Hold Time
Referenced to
RAS
RAS
Hold Time
Referenced to
OE
Access Time from
OE
Access Time from
CAS
(EDO)
Access Time from
RAS
Access Time from Column
Address
CAS
to Low-Z Output
Output buffer turn-off delay time
Column Address Hold Time
from
RAS
24
t
RL1AV
t
RAD
RAS
to Column Address
Delay Time
25
t
CL1RH1(W)
t
RSH (W)
RAS
or
CAS
Hold Time
in Write Cycle
Write Command to
CAS
Lead Time
12
12
13
14
11
17
12
20
13
23
14
26
0
0
28
6
40
45
50
V53C8258H
#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Min. Max. Min. Max. Min. Max. Min. Max. Unit
35
70
25
35
7
16
0
0
6
0
4
12
5
0
23
75K
40
75
25
40
8
17
0
0
7
0
5
12
5
0
28
75K
45
80
25
45
9
18
0
0
8
0
6
13
5
0
32
75K
50
90
30
50
9
19
0
0
9
0
7
14
5
0
36
75K
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
4
t
CL1RH1(R)
t
RSH (R)
t
CH2RL2
t
CH2WX
t
CRP
t
RCH
5
15
t
RH2WX
t
RRH
0
0
0
0
ns
5
16
t
OEL1RH2
t
ROH
8
8
9
10
ns
17
18
19
20
t
GL1QV
t
CL1QV
t
RL1QV
t
AVQV
t
OAC
t
CAC
t
RAC
t
CAA
12
12
35
18
12
12
40
20
13
13
45
22
14
14
50
24
ns
ns
ns
ns
6, 7
6, 8, 9
6, 7, 10
21
22
23
t
CL1QX
t
CH2QZ
t
RL1AX
t
LZ
t
HZ
t
AR
0
0
30
6
0
0
35
7
0
0
40
8
ns
ns
ns
16
16
ns
11
ns
26
t
WL1CH1
t
CWL
12
12
13
14
ns
V53C8258H Rev. 1.4 February 1997
5
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