54H53DMQB datasheet, PDF - EEWORLD Datasheet

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54H53DMQB: DescriptionAND-OR-Invert Gate, TTL/H/L Series, 1-Func, 9-Input, TTL, CDIP14, CERAMIC, DIP-14; Categorylogic logic; File Size54KB，2 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/

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54H53DMQB Overview

AND-OR-Invert Gate, TTL/H/L Series, 1-Func, 9-Input, TTL, CDIP14, CERAMIC, DIP-14

54H53DMQB Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Fairchild
Parts packaging code	DIP
package instruction	CERAMIC, DIP-14
Contacts	14
Reach Compliance Code	compliant
series	TTL/H/L
JESD-30 code	R-CDIP-T14
JESD-609 code	e0
Logic integrated circuit type	AND-OR-INVERT GATE
MaximumI(ol)	0.02 A
Number of functions	1
Number of entries	9
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Prop。Delay @ Nom-Sup	11 ns
Certification status	Not Qualified
Schmitt trigger	NO
Filter level	38535Q/M;38534H;883B
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	TTL
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	7.62 mm

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54H53DMQB Related Products

	54H53DMQB	5453DM	7453PC	7453FC	74H53FC	7453DC
Description	AND-OR-Invert Gate, TTL/H/L Series, 1-Func, 9-Input, TTL, CDIP14, CERAMIC, DIP-14	AND-OR-Invert Gate, TTL, CDIP14,	AND-OR-Invert Gate, TTL, PDIP14,	AND-OR-Invert Gate, TTL, CDFP14,	AND-OR-Invert Gate, TTL, CDFP14,	AND-OR-Invert Gate, TTL, CDIP14,
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	Fairchild	Fairchild	Fairchild	Fairchild	Fairchild	Fairchild
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant
JESD-30 code	R-CDIP-T14	R-XDIP-T14	R-PDIP-T14	R-XDFP-F14	R-XDFP-F14	R-XDIP-T14
JESD-609 code	e0	e0	e0	e0	e0	e0
Logic integrated circuit type	AND-OR-INVERT GATE	AND-OR-INVERT GATE	AND-OR-INVERT GATE	AND-OR-INVERT GATE	AND-OR-INVERT GATE	AND-OR-INVERT GATE
MaximumI(ol)	0.02 A	0.016 A	0.016 A	0.016 A	0.02 A	0.016 A
Number of terminals	14	14	14	14	14	14
Maximum operating temperature	125 °C	125 °C	70 °C	70 °C	70 °C	70 °C
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC	PLASTIC/EPOXY	CERAMIC	CERAMIC	CERAMIC
encapsulated code	DIP	DIP	DIP	DFP	DFP	DIP
Encapsulate equivalent code	DIP14,.3	DIP14,.3	DIP14,.3	FL14,.3	FL14,.3	DIP14,.3
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	IN-LINE	IN-LINE	FLATPACK	FLATPACK	IN-LINE
Prop。Delay @ Nom-Sup	11 ns	22 ns	22 ns	22 ns	11 ns	22 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Schmitt trigger	NO	NO	NO	NO	NO	NO
surface mount	NO	NO	NO	YES	YES	NO
technology	TTL	TTL	TTL	TTL	TTL	TTL
Temperature level	MILITARY	MILITARY	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	FLAT	FLAT	THROUGH-HOLE
Terminal pitch	2.54 mm	2.54 mm	2.54 mm	1.27 mm	1.27 mm	2.54 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
package instruction	CERAMIC, DIP-14	-	DIP, DIP14,.3	DFP, FL14,.3	DFP, FL14,.3	DIP, DIP14,.3
Is it lead-free?	-	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead
Humidity sensitivity level	-	2A	2A	2A	2A	2A
Peak Reflow Temperature (Celsius)	-	250	250	250	250	250
Maximum time at peak reflow temperature	-	30	30	30	30	30

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