Features
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EE Programmable 1,048,576 x 1-bit Serial Memory Designed to Store Configuration
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Programs for Field Programmable Gate Arrays (FPGAs)
Very Low-power CMOS EEPROM Process
In-System Programmable (ISP) via Two-Wire Bus
Simple Interface to SRAM FPGAs
Compatible with AT40K Devices
Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
Programmable Reset Polarity
Low-power Standby Mode
High-reliability
– Endurance: 5,10
4
Erase/Write Cycles
– Data Retention: 10 Years
No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm
2
@125°C
Tested up to a Total Dose of (according to MIL STD 883 Method 1019)
– 20 krads (Si) Read-only mode when Biased
– 60 krads (Si) Read-only mode when Unbiased
Operating Range: 3.0V to 3.6V, -55°C to +125°C
Available in 400 mils Wide 28 Pins DIL Flat Pack
Space FPGA
Configuration
EEPROM
AT17LV010-10DP
Description
The AT17LV010-10DP is a FPGA Configuration Serial EEPROM which provides an
easy-to-use, cost-effective configuration memory for Field Programmable Gate
Arrays. It is packaged in a 28-pin 400 mils wide Flat Pack package. The configurator
uses a simple serial link to configure one or more FPGA devices. The user can select
the polarity of the reset function by programming four EEPROM bytes. Since the
default setting is RESET low and OE high, this document will describe RESET/OE.
The device also supports a write-protection mechanism within its programming mode.
4265G–AERO–09/14
Block Diagram
SER_EN
WP1
WP2
PROGRAMMING
MODE LOGIC
PROGRAMMING
DATA SHIFT
REGISTER
POWER ON
RESET
ROW
ADDRESS
COUNTER
ROW
DECODER
EEPROM
CELL
MATRIX
BIT
COUNTER
TC
COLUMUN
DECODER
CLK READY
RESET/OE
CE
CEO (A2)
DATA
Device Description
The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) interface directly
with the FPGA device control signals. All FPGA devices can control the entire configuration pro-
cess and retrieve data from the configuration EEPROM without requiring an external intelligent
controller.
The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the DATA out-
put pin and enable the address counter. When RESET/OE is driven low, the configuration
EEPROM resets its address counter and tri-states its DATA pin. The CE pin also controls the
output of the configurator. If CE is held high after the RESET/OE reset pulse, the counter is dis-
abled and the DATA output pin is tri-stated. When RESET/OE is subsequently driven high, the
counter and the DATA output pin are enabled. When RESET/OE is driven low again, the
address counter is reset and the DATA output pin is tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven low, the device tri-states
the DATA pin to avoid contention with other configurators. Upon power-up, the address counter
is automatically reset.
2
AT17LV010-10DP
4265G–AERO–09/14
AT17LV010-10DP
Pin Configuration
RESET/OE
NC
WP2
CE
GND
NC
NC
NC
NC
Reserved
CE0(A2)
NC
NC
READY
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Reserved
NC
WP1
CLK
DATA
NC
NC
NC
NC
VCC
Reserved
SER_EN
NC
NC
Figure 1.
28-pin Flat Pack
Note:
Package lid is NOT connected to GND
Pin Description
RESET
/ OE
Output Enable (active high) and RESET (active low) when SER_EN is high. A low level on
RESET/OE resets both the address and bit counters. A high level (with CE low) enables the data
output driver. The logic polarity of this input is programmable as either RESET/OE or
RESET/OE. Since almost all FPGAs use RESET low and OE high, this document describes the
pin as RESET/OE. This is the default setting for the device.
WRITE PROTECT (2). Used to protect portions of memory during programming. Disabled
by default due to internal pull-down resistor. This input pin is not used during FPGA loading
operations.
Chip Enable input (active low). A low level (with RESET/OE high) allows CLK to increment the
address counter and enables the data output driver. A high level on CE disables both the
address and bit counters and forces the device into a low-power standby mode. Note that this
pin
does not
enable/disable the device in the Two-Wire Serial Programming mode (SER_EN
low).
Chip Enable Output (active low). This output goes low when the address counter has reached its
maximum value. In a daisy chain of AT17LV010-10DP devices, the CEO pin of one device must
be connected to the CE input of the next device in the chain. It stays low as long as CE is low
and RESET/OE is high. It then follows CE until RESET/OE goes low. Thereafter, CEO stays
high until the entire EEPROM is read again.
WP2
CE
CEO
3
4265G–AERO–09/14
A2
READY
SER_EN
Device selection input. This is used to enable (or select) the device during programming (i.e.,
when SER_EN is low). This pin has an internal pull-down resistor.
Open collector reset state indicator. Driven low during power-up reset, released when power-up
is complete. It is recommended to use a 4.7 kΩ pull-up resistor when this pin is used.
Serial enable must be held high during FPGA loading operations. Bringing SER_EN low enables
the Two-Wire Serial Programming Mode. For non-ISP applications, SER_EN should be tied to
V
CC
.
Tri-state DATA output for configuration. Open-collector bi-directional pin for programming.
Clock input. Used to increment the internal address and bit counter for reading and
programming.
WRITE PROTECT (1). Used to protect portions of memory during programming. Disabled
by default due to internal pull-down resistor. This input pin is not used during FPGA loading
operations.
3.3V (±0.3V). A 0.2
µF
decoupling capacitor between V
CC
and GND is recommended
Ground pin.
These pins are not connected internally. It is recommended to connect them to a power supply
(GND or Vcc).
These pins are connected internally for manufacturing testing - DO NOT CONNECT.
DATA
CLK
WP1
V
CC
GND
NC
Reserved
4
AT17LV010-10DP
4265G–AERO–09/14
AT17LV010-10DP
FPGA Master Serial Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration pro-
gram. The program is loaded either automatically upon power-up, or on command, depending
on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the config-
uration program from an external memory. The Serial Configuration EEPROM has been
designed for compatibility with the Master Serial mode.
This section discusses the Atmel AT40KEL applications.
Control of Configuration
Most connections between the FPGA device and the Serial EEPROM are simple and self-
explanatory.
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The DATA output of the configurator drives the DATA input of the FPGA devices.
The master FPGA CCLK output drives the CLK input of the configurator.
The FPGA CON output drives the CE input of the configurator.
The FPGA INIT output drives the RESET/OE input of the configurator.
The A2 input of the configurator must be left unconnected (thanks to the internal pull down
resistor) or tied to Vcc depending on the TWI address configuration.
SER_EN must be connected to V
CC
(except during ISP).
The READY pin is available as an open-collector indicator of the device’s reset status; it is
driven low while the device is in its power-on reset cycle and released (tri-stated) when the
cycle is complete.
Figure 2.
Single Device Configuration Schematic
4.7 K
4.7 K
In-System
Programming
interface
DATA
CLK
4.7 K
RESETn
4.7 K
SER_EN
A2/CEO
READY
CS0
AT17LV010
DATA
CLK
CE
RESET/OE
5
4265G–AERO–09/14
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