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INTEGRATED CIRCUITS
DATA SHEET
74AVC16373
16-bit D-type transparent latch;
3.6 V tolerant; 3-state
Product Specification
Supersedes data of 1998 Dec 11
File under Integrated Circuits, IC24
2000 Mar 09
Philips Semiconductors
Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
FEATURES
•
Wide supply voltage range from 1.2 to 3.6 V
•
Complies with JEDEC standard no. 8-1A/5/7
•
CMOS low power consumption
•
Input/output tolerant up to 3.6 V
•
Dynamic Controlled Output (DCO) circuit dynamically
changes output impedance, resulting in noise reduction
without speed degradation
•
Low inductance multiple V
CC
and GND pins to minimize
noise and ground bounce
•
Supports Live Insertion.
DESCRIPTION
74AVC16373
The 74AVC16373 is a 16-bit D-type transparent latch
featuring separate D-type inputs for each latch, and
3-state outputs for bus oriented applications. One Latch
Enable (LE) input and one Output Enable (OE) input are
provided per 8-bit section. The 74AVC16373 consist of
two sections of eight D-type transparent latches with
3-state true outputs.
The 74AVC16373 is designed to have an extremely fast
propagation delay and a minimum amount of power
consumption.
To ensure the high-impedance output state during
power-up or power-down, pin OE
n
should be tied to V
CC
through a pull-up resistor (Live Insertion).
A Dynamic Controlled Output (DCO) circuitry is
implemented to support termination line drive during
transient (see Figs 1 and 2).
MNA506
MNA507
handbook, halfpage
0
handbook, halfpage
300
I OH
(mA)
1.8 V
−100
I OL
(mA)
200
2.5 V
2.5 V
3.3 V
−200
100
1.8 V
3.3 V
−300
0
0
1
2
3
VOH (V)
4
0
1
2
3
VOL (V)
4
Fig.1
Output voltage as a function of the
HIGH-level output current.
Fig.2
Output voltage as a function of the
LOW-level output current.
2000 Mar 09
2
Philips Semiconductors
Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
2.0 ns.
SYMBOL
t
PHL
/t
PLH
PARAMETER
propagation delay
nD
n
to nQ
n
CONDITIONS
V
CC
= 1.2 V
V
CC
= 1.5 V
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 3.3 V
C
I
C
PD
input capacitance
power dissipation
capacitance per buffer
notes 1 and 2
outputs enabled
outputs disabled
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
2. The condition is V
I
= GND to V
CC
.
FUNCTION TABLE
See note 1.
INPUTS
OPERATING MODES
nOE
Enable and read register
(transparent mode)
Latch and read register
(hold mode)
Latch register and disable outputs
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high impedance OFF-state.
L
L
L
L
H
H
LE
H
H
L
L
L
L
nA
n
L
H
l
h
l
h
INTERNAL
LATCHES
L
H
L
H
L
H
34
1
3.6
3.1
2.2
1.6
1.4
5.0
74AVC16373
TYP.
ns
ns
ns
ns
ns
pF
pF
pF
UNIT
OUTPUTS
nY
n
L
H
L
H
Z
Z
2000 Mar 09
3
Philips Semiconductors
Product Specification
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
ORDERING AND PACKAGE INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE RANGE
74AVC16373DGG
PINNING
PIN
1
2, 3, 5, 6, 8, 9, 11 and 12
4, 10, 15, 21, 28, 34, 39 and 45
7, 18, 31 and 42
13, 14, 16, 17, 19, 20, 22 and 23
24
25
26, 27, 29, 30, 32, 33, 35 and 36
37, 38, 40, 41, 43, 44, 46 and 47
48
SYMBOL
1OE
1Q
0
to 1Q
7
GND
V
CC
2Q
0
to 2Q
7
2OE
2LE
2D
7
to 2D
0
1D
7
to 1D
0
1LE
data outputs
ground (0 V)
DC supply voltage
data outputs
−40
to +85
°C
PINS
48
PACKAGE
TSSOP
74AVC16373
MATERIAL
plastic
CODE
SOT362-1
DESCRIPTION
output enable input (active LOW)
output enable input (active LOW)
latch enable input (active HIGH)
data inputs
data inputs
latch enable input (active HIGH)
2000 Mar 09
4
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