SHARC Processor
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
SUMMARY
High performance signal processor for communications,
graphics and imaging applications
Super Harvard Architecture
4 independent buses for dual data fetch, instruction fetch,
and nonintrusive I/O
32-bit IEEE floating-point computation units—multiplier,
ALU, and shifter
Dual-ported on-chip SRAM and integrated I/O peripherals—a
complete system-on-a-chip
Integrated multiprocessing features
240-lead thermally enhanced MQFP_PQ4 package, 225-ball
plastic ball grid array (PBGA), 240-lead hermetic CQFP
package
RoHS compliant packages
KEY FEATURES—PROCESSOR CORE
40 MIPS, 25 ns instruction rate, single-cycle instruction
execution
120 MFLOPS peak, 80 MFLOPS sustained performance
Dual data address generators with modulo and bit-reverse
addressing)
Efficient program sequencing with zero-overhead looping:
Single-cycle loop setup
IEEE JTAG Standard 1149.1 Test Access Port and on-chip
emulation
32-bit single-precision and 40-bit extended-precision IEEE
floating-point data formats or 32-bit fixed-point data
format
CORE PROCESSOR
INSTRUCTION
CACHE
32 48-BIT
DUAL-PORTED SRAM
B LOCK 0
TWO INDEPENDENT
DUAL-PORTED BLOCKS
JTAG
BLOCK 1
TEST AND
EMULATION
7
TIMER
8
DAG1
4 32
8
DAG2
4 24
PROCESSOR PORT
I/O PORT
ADDR
DATA
ADDR
DATA
DATA
ADDR
ADDR
DATA
PROGRAM
SEQUENCER
24
32
IOD
48
IOA
17
EXTERNAL
PORT
32
PM ADDRESS BUS
DM ADDRESS BUS
ADDR BUS
MUX
MULTIPROCESSOR
INTERFACE
PM DATA BUS
BUS
CONNECT
(PX)
DM DATA BUS
48
40/32
DATA BUS
MUX
48
S
DATA
REGISTER
FILE
MULT
16
40-BIT
BARREL
SHIFTER
ALU
IOP
REGISTERS
(MEMORY
MAPPED)
CONTROL,
STATUS AND
DATA BUFFERS
DMA
CONTROLLER
SERIAL PORTS
(2)
LINK PORTS
(6)
HOST PORT
4
6
6
36
I/O PROCESSOR
Figure 1. Functional Block Diagram
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
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Tel : 781.329.4700
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Fax: 781.461.3113
©2008
Analog Devices, Inc. All rights reserved.
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
PROCESSOR FEATURES (Continued)
The processor family provides a variety of features. For a com-
parison across family members, see
Table 1.
HOST PROCESSOR INTERFACE TO 16- AND 32-BIT
MICROPROCESSORS
Host can directly read/write ADSP-2106x internal memory
and IOP registers
PARALLEL COMPUTATIONS
Single-cycle multiply and ALU operations in parallel with
dual memory read/writes and instruction fetch
Multiply with add and subtract for accelerated FFT butterfly
computation
MULTIPROCESSING
Glueless connection for scalable DSP multiprocessing
architecture
Distributed on-chip bus arbitration for parallel bus connect
of up to six ADSP-2106xs plus host
6
link ports for point-to-point connectivity and array
multiprocessing
240 MBps transfer rate over parallel bus
240 MBps transfer rate over link ports
UP TO 4M BIT ON-CHIP SRAM
Dual-ported for independent access by core processor and
DMA
OFF-CHIP MEMORY INTERFACING
4 gigawords addressable
Programmable wait state generation, page-mode DRAM
support
SERIAL PORTS
Two 40 Mbps synchronous serial ports with companding
hardware
Independent transmit and receive functions
DMA CONTROLLER
10 DMA channels for transfers between ADSP-2106x internal
memory and external memory, external peripherals, host
processor, serial ports, or link ports
Background DMA transfers at up to 40 MHz, in parallel with
full-speed processor execution
Table 1. ADSP-2106x SHARC Processor Family Features
Feature
SRAM
Operating
Voltage
Instruction
Rate
Package
ADSP-21060
4M bits
5V
33 MHz
40 MHz
MQFP_PQ4
PBGA
ADSP-21062
2M bits
5V
33 MHz
40 MHz
MQFP_PQ4
PBGA
ADSP-21060L
4M bits
3.3 V
33 MHz
40 MHz
MQFP_PQ4
PBGA
ADSP-21062L
2M bits
3.3 V
33 MHz
40 MHz
MQFP_PQ4
PBGA
ADSP-21060C
4M bits
5V
33 MHz
40 MHz
CQFP
ADSP-21060LC
4M bits
3.3 V
33 MHz
40 MHz
CQFP
Rev. F
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March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
CONTENTS
Summary ............................................................... 1
Key Features—Processor Core .................................... 1
Processor Features (Continued) .................................. 2
Parallel Computations .............................................. 2
Up to 4M Bit On-Chip SRAM ..................................... 2
Off-Chip Memory Interfacing ..................................... 2
DMA Controller ...................................................... 2
Host Processor Interface to 16- and 32-Bit Microprocessors 2
Multiprocessing ....................................................... 2
Serial Ports ............................................................. 2
Contents ................................................................ 3
Revision History ...................................................... 3
General Description ................................................. 4
SHARC Family Core Architecture ............................ 4
Memory and I/O Interface Features ........................... 5
Development Tools ............................................... 8
Evaluation Kit ...................................................... 9
Designing an Emulator-Compatible DSP Board (Target) 9
Additional Information .......................................... 9
Pin Function Descriptions ........................................ 10
Target Board Connector for EZ-ICE Probe ................ 13
ADSP-21060/ADSP-21062 Specifications ..................... 15
Operating Conditions (5 V) ................................... 15
Electrical Characteristics (5 V) ................................ 15
Internal Power Dissipation (5 V) ............................. 16
External Power Dissipation (5 V) ............................ 17
ADSP-21060L/ADSP-21062L Specifications ................. 18
Operating Conditions (3.3 V) ................................. 18
Electrical Characteristics (3.3 V) ............................. 18
Internal Power Dissipation (3.3 V) .......................... 19
External Power Dissipation (3.3 V) .......................... 20
Absolute Maximum Ratings ................................... 20
ESD Caution ...................................................... 21
Package Marking Information ................................ 21
Timing Specifications ........................................... 21
Test Conditions .................................................. 47
Environmental Conditions .................................... 50
225-Ball PBGA Ball Configurations ............................ 51
240-Lead MQFP_PQ4/CQFP Pin Configurations ........... 53
Outline Dimensions ................................................ 55
Surface-Mount Design .......................................... 60
Ordering Guide ..................................................... 61
REVISION HISTORY
3/08—Rev. E to Rev. F
Revised Absolute Maximum Ratings ............................
20
Corrected model package descriptions.
See Ordering Guide..................................................
61
Rev. F
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March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
GENERAL DESCRIPTION
The ADSP-2106x SHARC
®
—Super Harvard Architecture Com-
puter—is a 32-bit signal processing microcomputer that offers
high levels of DSP performance. The ADSP-2106x builds on the
ADSP-21000 DSP core to form a complete system-on-a-chip,
adding a dual-ported on-chip SRAM and integrated I/O periph-
erals supported by a dedicated I/O bus.
Fabricated in a high speed, low power CMOS process, the
ADSP-2106x has a 25 ns instruction cycle time and operates at
40 MIPS. With its on-chip instruction cache, the processor can
execute every instruction in a single cycle.
Table 2
shows perfor-
mance benchmarks for the ADSP-2106x.
The ADSP-2106x SHARC represents a new standard of integra-
tion for signal computers, combining a high performance
floating-point DSP core with integrated, on-chip system fea-
tures including up to 4M bit SRAM memory (see
Table 1),
a
host processor interface, DMA controller, serial ports and link
port, and parallel bus connectivity for glueless DSP
multiprocessing.
Table 2. Benchmarks (at 40 MHz)
Benchmark Algorithm
1024 Point Complex FFT (Radix 4, with
reversal)
FIR Filter (per tap)
IIR Filter (per biquad)
Divide (y/x)
Inverse Square Root
DMA Transfer Rate
Speed
0.46
Ps
25 ns
100 ns
150 ns
225 ns
240 Mbytes/s
Cycles
18,221
1
4
6
9
• Serial ports and link ports
• JTAG Test Access Port
ADSP-2106x
1
CLOCK
CLKIN
EBOOT
3
4
LBOOT
IRQ2–0
FLAG3–0
TIMEXP
LINK
DEVICES
(6 MAX)
(OPTIONAL)
LxCLK
LxACK
LxDAT3–0
TCLK0
RCLK0
TFS0
RSF0
DT0
DR0
TCLK1
RCLK1
TFS1
RSF1
DT1
DR1
RPBA
ID2–0
RESET
ADDR31–0
DATA47–0
RD
WR
ACK
MS3–0
CONTROL
DATA
BMS
CS
ADDR
DATA
ADDR
BOOT
EPROM
(OPTIONAL)
DATA MEMORY-
MAPPED
OE
DEVICES
WE
(OPTIONAL)
ACK
CS
ADDRESS
PAGE
SBTS
ADRCLK
DMAR1–2
DMAG1–2
CS
HBR
HBG
REDY
BR1–6
PA
JTAG
6
SERIAL
DEVICE
(OPTIONAL)
DMA DEVICE
(OPTIONAL)
DATA
SERIAL
DEVICE
(OPTIONAL)
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
ADDR
DATA
Figure 2. ADSP-2106x System Sample Configuration
SHARC FAMILY CORE ARCHITECTURE
The ADSP-2106x continues SHARC’s industry-leading stan-
dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features.
The block diagram
on Page 1
illustrates the following architec-
tural features:
• Computation units (ALU, multiplier and shifter) with a
shared data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro-
cessor cycle
• Interval timer
• On-chip SRAM
• External port for interfacing to off-chip memory and
peripherals
• Host port and multiprocessor Interface
• DMA controller
The ADSP-2106x includes the following architectural features
of the ADSP-21000 family core. The ADSP-2106x processors
are code- and function-compatible with the ADSP-21020.
Independent, Parallel Computation Units
The arithmetic/logic unit (ALU), multiplier and shifter all per-
form single-cycle instructions. The three units are arranged in
parallel, maximizing computational throughput. Single multi-
function instructions execute parallel ALU and multiplier oper-
ations. These computation units support IEEE 32-bit single-
precision floating-point, extended precision 40-bit floating-
point, and 32-bit fixed-point data formats.
Data Register File
A general–purpose data register file is used for transferring data
between the computation units and the data buses, and for stor-
ing intermediate results. This 10-port, 32-register (16 primary,
16 secondary) register file, combined with the ADSP-21000
Harvard architecture, allows unconstrained data flow between
computation units and internal memory.
Rev. F
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March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Single-Cycle Fetch of Instruction and Two Operands
The ADSP-2106x features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see
Figure 1 on Page 1).
With its separate program and data
memory buses and on-chip instruction cache, the processor can
simultaneously fetch two operands and an instruction (from the
cache), all in a single cycle.
On the ADSP-21060/ADSP-21060L, the memory can be config-
ured as a maximum of 128k words of 32-bit data, 256k words of
16-bit data, 80k words of 48-bit instructions (or 40-bit data), or
combinations of different word sizes up to four megabits. All of
the memory can be accessed as 16-bit, 32-bit or 48-bit words.
A 16-bit floating-point storage format is supported, which effec-
tively doubles the amount of data that can be stored on-chip.
Conversion between the 32-bit floating-point and 16-bit float-
ing-point formats is done in a single instruction.
While each memory block can store combinations of code and
data, accesses are most efficient when one block stores data,
using the DM bus for transfers, and the other block stores
instructions and data, using the PM bus for transfers. Using the
DM bus and PM bus in this way, with one dedicated to each
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache. Single-cycle execution is also maintained when one of the
data operands is transferred to or from off-chip, via the
ADSP-2106x’s external port.
Instruction Cache
The ADSP-2106x includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and two
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
allows full-speed execution of core, looped operations such as
digital filter multiply-accumulates and FFT butterfly processing.
Data Address Generators with Hardware Circular Buffers
The ADSP-2106x’s two data address generators (DAGs) imple-
ment circular data buffers in hardware. Circular buffers allow
efficient programming of delay lines and other data structures
required in digital signal processing, and are commonly used in
digital filters and Fourier transforms. The two DAGs of the
ADSP-2106x contain sufficient registers to allow the creation of
up to 32 circular buffers (16 primary register sets, 16 secondary).
The DAGs automatically handle address pointer wraparound,
reducing overhead, increasing performance and simplifying
implementation. Circular buffers can start and end at any mem-
ory location.
On-Chip Memory and Peripherals Interface
The ADSP-2106x’s external port provides the processor’s inter-
face to off-chip memory and peripherals. The 4-gigaword off-
chip address space is included in the ADSP-2106x’s unified
address space. The separate on-chip buses—for PM addresses,
PM data, DM addresses, DM data, I/O addresses, and I/O
data—are multiplexed at the external port to create an external
system bus with a single 32-bit address bus and a single 48-bit
(or 32-bit) data bus.
Addressing of external memory devices is facilitated by on-chip
decoding of high-order address lines to generate memory bank
select signals. Separate control lines are also generated for sim-
plified addressing of page-mode DRAM. The ADSP-2106x
provides programmable memory wait states and external mem-
ory acknowledge controls to allow interfacing to DRAM and
peripherals with variable access, hold and disable time
requirements.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of
parallel operations, for concise programming. For example, the
ADSP-2106x can conditionally execute a multiply, an add, a
subtract and a branch, all in a single instruction.
MEMORY AND I/O INTERFACE FEATURES
The ADSP-2106x processors add the following architectural
features to the SHARC family core.
Host Processor Interface
The ADSP-2106x’s host interface allows easy connection to
standard microprocessor buses, both 16-bit and 32-bit, with lit-
tle additional hardware required. Asynchronous transfers at
speeds up to the full clock rate of the processor are supported.
The host interface is accessed through the ADSP-2106x’s exter-
nal port and is memory-mapped into the unified address space.
Four channels of DMA are available for the host interface; code
and data transfers are accomplished with low software
overhead.
The host processor requests the ADSP-2106x’s external bus with
the host bus request (HBR), host bus grant (HBG), and ready
(REDY) signals. The host can directly read and write the inter-
nal memory of the ADSP-2106x, and can access the DMA
channel setup and mailbox registers. Vector interrupt support is
provided for efficient execution of host commands.
Dual-Ported On-Chip Memory
The ADSP-21062/ADSP-21062L contains two megabits of on-
chip SRAM, and the ADSP-21060/ADSP-21060L contains
4M bits of on-chip SRAM. The internal memory is organized as
two equal sized blocks of 1M bit each for the ADSP-21062/
ADSP-21062L and two equal sized blocks of 2M bits each for
the ADSP-21060/ADSP-21060L. Each can be configured for dif-
ferent combinations of code and data storage. Each memory
block is dual-ported for single-cycle, independent accesses by
the core processor and I/O processor or DMA controller. The
dual-ported memory and separate on-chip buses allow two data
transfers from the core and one from I/O, all in a single cycle.
On the ADSP-21062/ADSP-21062L, the memory can be config-
ured as a maximum of 64k words of 32-bit data, 128k words of
16-bit data, 40k words of 48-bit instructions (or 40-bit data), or
combinations of different word sizes up to two megabits. All of
the memory can be accessed as 16-bit, 32-bit, or 48-bit words.
Rev. F
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March 2008
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