ASDP-21060CW-160 datasheet, PDF

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ASDP-21060CW-160: Description48-BIT, 40 MHz, OTHER DSP, CQFP240; Categorysemiconductor The embedded processor and controller; File Size621KB，64 Pages; ManufacturerADI; Websitehttps://www.analog.com

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ASDP-21060CW-160 Overview

48-BIT, 40 MHz, OTHER DSP, CQFP240

ASDP-21060CW-160 Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	240
Maximum operating temperature	100 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	5.25 V
Minimum supply/operating voltage	4.75 V
Rated supply voltage	5 V
External data bus width	48
Processing package description	THERMALLY ENHANCED, HEAT SINK, Ceramic, Quad Flat Package-240
Lead-free	Yes
EU RoHS regulations	Yes
China RoHS regulations	Yes
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	FLATPACK, HEAT SINK/SLUG, FINE PITCH
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.5000 mm
terminal coating	Gold OVER Nickel
Terminal location	Four
Packaging Materials	Ceramic, Metal-SEALED COFIRED
Temperature level	INDUSTRIAL
Address bus width	32
barrel shifter	Yes
boundary scan	Yes
Maximum FCLK clock frequency	40 MHz
floating point unit	Yes
Internal bus architecture	many
low power mode	Yes
Microprocessor type	Other digital signal processors
Number of data processing bits	32

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SHARC Processor

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

SUMMARY

High performance signal processor for communications,

graphics and imaging applications

Super Harvard Architecture

4 independent buses for dual data fetch, instruction fetch,

and nonintrusive I/O

32-bit IEEE floating-point computation units—multiplier,

ALU, and shifter

Dual-ported on-chip SRAM and integrated I/O peripherals—a

complete system-on-a-chip

Integrated multiprocessing features

240-lead thermally enhanced MQFP_PQ4 package, 225-ball

plastic ball grid array (PBGA), 240-lead hermetic CQFP

package

RoHS compliant packages

KEY FEATURES—PROCESSOR CORE

40 MIPS, 25 ns instruction rate, single-cycle instruction

execution

120 MFLOPS peak, 80 MFLOPS sustained performance

Dual data address generators with modulo and bit-reverse

addressing)

Efficient program sequencing with zero-overhead looping:

Single-cycle loop setup

IEEE JTAG Standard 1149.1 Test Access Port and on-chip

emulation

32-bit single-precision and 40-bit extended-precision IEEE

floating-point data formats or 32-bit fixed-point data

format

CORE PROCESSOR

INSTRUCTION

CACHE

32 48-BIT

DUAL-PORTED SRAM

B LOCK 0

TWO INDEPENDENT

DUAL-PORTED BLOCKS

JTAG

BLOCK 1

TEST AND

EMULATION

TIMER

DAG1

4 32

DAG2

4 24

PROCESSOR PORT

I/O PORT

ADDR

DATA

ADDR

DATA

ADDR

DATA

PROGRAM

SEQUENCER

IOD

IOA

EXTERNAL

PORT

PM ADDRESS BUS

DM ADDRESS BUS

ADDR BUS

MUX

MULTIPROCESSOR

INTERFACE

PM DATA BUS

BUS

CONNECT

(PX)

DM DATA BUS

40/32

DATA BUS

MUX

DATA

FILE

MULT

40-BIT

BARREL

SHIFTER

ALU

IOP

REGISTERS

(MEMORY

MAPPED)

CONTROL,

STATUS AND

DATA BUFFERS

DMA

CONTROLLER

SERIAL PORTS

(2)

LINK PORTS

(6)

HOST PORT

I/O PROCESSOR

Figure 1. Functional Block Diagram

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel : 781.329.4700

www.analog.com

Fax: 781.461.3113

ASDP-21060CW-160 Related Products

	ASDP-21060CW-160	ADSP-21060LKBZ-160	ASDP-21060CZ-1601	ASDP-21060CW-133	ASDP-21060CWZ-133	ASDP-21060CZ-133	ASDP-21060CZZ-133	ASDP-21060CZZ-160	ASDP-21060LCW-160
Description	48-BIT, 40 MHz, OTHER DSP, CQFP240	48-BIT, 40 MHz, OTHER DSP, CQFP240	48-BIT, 40 MHz, OTHER DSP, CQFP240	48-BIT, 40 MHz, OTHER DSP, CQFP240	48-BIT, 40 MHz, OTHER DSP, CQFP240	48-BIT, 40 MHz, OTHER DSP, CQFP240	48-BIT, 40 MHz, OTHER DSP, CQFP240	48-BIT, 40 MHz, OTHER DSP, CQFP240	48-BIT, 40 MHz, OTHER DSP, CQFP240
Number of functions	1	1	1	1	1	1	1	1	1
Number of terminals	240	240	240	240	240	240	240	240	240
Maximum operating temperature	100 Cel	100 Cel	100 Cel	100 Cel	100 Cel	100 Cel	100 Cel	100 Cel	100 Cel
Minimum operating temperature	-40 Cel	-40 Cel	-40 Cel	-40 Cel	-40 Cel	-40 Cel	-40 Cel	-40 Cel	-40 Cel
Maximum supply/operating voltage	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V
Minimum supply/operating voltage	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V
Rated supply voltage	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
External data bus width	48	48	48	48	48	48	48	48	48
Processing package description	THERMALLY ENHANCED, HEAT SINK, Ceramic, Quad Flat Package-240	THERMALLY ENHANCED, HEAT SINK, Ceramic, Quad Flat Package-240	THERMALLY ENHANCED, HEAT SINK, Ceramic, Quad Flat Package-240	THERMALLY ENHANCED, HEAT SINK, Ceramic, Quad Flat Package-240	THERMALLY ENHANCED, HEAT SINK, Ceramic, Quad Flat Package-240	THERMALLY ENHANCED, HEAT SINK, Ceramic, Quad Flat Package-240	THERMALLY ENHANCED, HEAT SINK, Ceramic, Quad Flat Package-240	THERMALLY ENHANCED, HEAT SINK, Ceramic, Quad Flat Package-240	THERMALLY ENHANCED, HEAT SINK, Ceramic, Quad Flat Package-240
Lead-free	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes
EU RoHS regulations	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes
China RoHS regulations	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes
state	ACTIVE	ACTIVE	ACTIVE	ACTIVE	ACTIVE	ACTIVE	ACTIVE	ACTIVE	ACTIVE
Craftsmanship	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
packaging shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package Size	FLATPACK, HEAT SINK/SLUG, FINE PITCH	FLATPACK, HEAT SINK/SLUG, FINE PITCH	FLATPACK, HEAT SINK/SLUG, FINE PITCH	FLATPACK, HEAT SINK/SLUG, FINE PITCH	FLATPACK, HEAT SINK/SLUG, FINE PITCH	FLATPACK, HEAT SINK/SLUG, FINE PITCH	FLATPACK, HEAT SINK/SLUG, FINE PITCH	FLATPACK, HEAT SINK/SLUG, FINE PITCH	FLATPACK, HEAT SINK/SLUG, FINE PITCH
surface mount	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal spacing	0.5000 mm	0.5000 mm	0.5000 mm	0.5000 mm	0.5000 mm	0.5000 mm	0.5000 mm	0.5000 mm	0.5000 mm
terminal coating	Gold OVER Nickel	Gold OVER Nickel	Gold OVER Nickel	Gold OVER Nickel	Gold OVER Nickel	Gold OVER Nickel	Gold OVER Nickel	Gold OVER Nickel	Gold OVER Nickel
Terminal location	Four	Four	Four	Four	Four	Four	Four	Four	Four
Packaging Materials	Ceramic, Metal-SEALED COFIRED	Ceramic, Metal-SEALED COFIRED	Ceramic, Metal-SEALED COFIRED	Ceramic, Metal-SEALED COFIRED	Ceramic, Metal-SEALED COFIRED	Ceramic, Metal-SEALED COFIRED	Ceramic, Metal-SEALED COFIRED	Ceramic, Metal-SEALED COFIRED	Ceramic, Metal-SEALED COFIRED
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Address bus width	32	32	32	32	32	32	32	32	32
barrel shifter	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes
boundary scan	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes
Maximum FCLK clock frequency	40 MHz	40 MHz	40 MHz	40 MHz	40 MHz	40 MHz	40 MHz	40 MHz	40 MHz
floating point unit	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes
Internal bus architecture	many	many	many	many	many	many	many	many	many
low power mode	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes
Microprocessor type	Other digital signal processors	Other digital signal processors	Other digital signal processors	Other digital signal processors	Other digital signal processors	Other digital signal processors	Other digital signal processors	Other digital signal processors	Other digital signal processors
Number of data processing bits	32	32	32	32	32	32	32	32	32

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