0
R
XC95144XV High-Performance
CPLD
0
1
DS051 (v2.0) January 25, 2001
Advance Product Specification
Features
•
•
144 macrocells with 3,200 usable gates
Available in small footprint packages
- 100-pin TQFP (81 user I/O pins)
- 144-pin TQFP (117 user I/O pins)
- 144-pin CSP (117 user I/O pins)
Optimized for high-performance 2.5V systems
- Low power operation
- Multi-voltage operation
Advanced system features
- In-system programmable
- Two separate output banks
- Superior pin-locking and routability with
FastCONNECT II™ switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold ciruitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
- Endurance exceeding 10,000 program/erase
cycles
- 20 year data retention
- ESD protection exceeding 2,000V
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XV device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of I
CC
, the following equation may be
used:
I
CC
(mA) = MC
HP
(0.5) + MC
LP
(0.3) + MC(0.0045 mA/MHz) f
Where:
MC
HP
= Macrocells in high-performance (default) mode
MC
LP
= Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
This calculation is based on typical operating conditions
using a pattern of 16-bit up/down counters in each Function
Block with no output loading. The actual I
CC
value varies
with the design application and should be verified during
normal system operation.
Figure 1
shows the above estimation in a graphical form.
200
200 MHz
•
•
•
•
•
•
150
Typical ICC (mA)
ce
r
100
Hi g
h
r
Pe
Lo
m
for
an
120 MHz
o
wP
we
Description
The XC95144XV is a 2.5V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of eight
54V18 Function Blocks, providing 3,200 usable gates with
propagation delays of 4 ns.
50
0
40
80
120
160
200
Clock Frequency (MHz)
DS051_01_012501
Figure 1:
Typical I
CC
vs. Frequency for XC95144XV
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS051 (v2.0) January 25, 2001
Advance Product Specification
www.xilinx.com
1-800-255-7778
1
XC95144XV High-Performance CPLD
R
3
JTAG Port
1
JTAG
Controller
In-System Programming Controller
54
I/O
I/O
I/O
FastCONNECT II Switch Matrix
I/O
54
18
18
Function
Block 1
Macrocells
1 to 18
Function
Block 2
Macrocells
1 to 18
I/O
Blocks
I/O
I/O
I/O
I/O
3
I/O/GCK
1
I/O/GSR
I/O/GTS
4
54
18
Function
Block 3
Macrocells
1 to 18
54
18
Function
Block 4
Macrocells
1 to 18
54
18
Function
Block 8
Macrocells
1 to 18
DS051_02_041000
Figure 2:
XC95144XV Architecture
Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.
2
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1-800-255-7778
DS051 (v2.0) January 25, 2001
Advance Product Specification
R
XC95144XV High-Performance CPLD
Absolute Maximum Ratings
Symbol
V
CC
V
CCIO
V
IN
V
TS
T
STG
T
SOL
T
J
Description
Supply voltage relative to GND
Supply voltage for output drivers
Input voltage relative to GND
(1)
Voltage applied to 3-state output
(1)
Storage temperature (ambient)
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm)
Junction temperature
Value
–0.5 to 2.7
–0.5 to 3.6
–0.5 to 3.6
–0.5 to 3.6
–65 to +150
+260
+150
Units
V
V
V
V
o
C
o
C
o
C
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the
device pins may undershoot to –2.0V or overshoot to +3.6V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Recommended Operation Conditions
Symbol
V
CCINT
Parameter
Supply voltage for internal logic
and input buffers
Commercial T
A
= 0
o
C to +70
o
C
Industrial T
A
= –40
o
C to +85
o
C
Min
2.4
2.4
3.1
2.4
1.7
0
1.7
0
Max
2.6
2.6
3.5
2.6
1.9
0.8
3.6
V
CCIO
V
V
V
V
V
V
Units
V
V
CCIO
Supply voltage for output drivers for 3.3V operation
Supply voltage for output drivers for 2.5V operation
Supply voltage for output drivers for 1.8V operation
V
IL
V
IH
V
O
Low-level input voltage
High-level input voltage
Output voltage
Quality and Reliability Characteristics
Symbol
T
DR
N
PE
V
ESD
Data retention
Program/Erase cycles (endurance)
Electrostatic Discharge (ESD)
Parameter
Min
20
10,000
2,000
Max
-
-
-
Units
Years
Cycles
Volts
DS051 (v2.0) January 25, 2001
Advance Product Specification
www.xilinx.com
1-800-255-7778
3
XC95144XV High-Performance CPLD
R
DC Characteristics
(Over Recommended Operating Conditions)
Symbol
V
OH
Parameter
Output high voltage for 3.3V outputs
Output high voltage for 2.5V outputs
Output high voltage for 1.8V outputs
V
OL
Output low voltage for 3.3V outputs
Output low voltage for 2.5V outputs
Output low voltage for 1.8V outputs
I
IL
Input leakage current
Test Conditions
I
OH
= –4.0 mA
I
OH
= –1.0 mA
I
OH
= –100
µA
I
OL
= 8.0 mA
I
OL
= 1.0 mA
I
OL
= 100
µA
V
CC
= 2.6V
V
CCIO
= 3.6V
V
IN
= GND or 3.6V
V
CC
= 2.0V
V
CCIO
= 3.6V
V
IN
= GND or 3.6V
V
IN
= GND
f = 1.0 MHz
V
I
= GND, No load
f = 1.0 MHz
Min
2.4
2.0
90% V
CCIO
-
-
-
-
Max
-
-
-
0.4
0.4
0.4
10
Units
V
V
V
V
V
V
µA
I
IH
I/O high-Z leakage current
-
10
µA
C
IN
I
CC
I/O capacitance
Operating Supply Current
(low power mode, active)
-
29
10
pF
mA
AC Characteristics
XC95144XV-4
Symbol
T
PD
T
SU
T
H
T
CO
f
SYSTEM
T
PSU
T
PH
T
PCO
T
OE
T
OD
T
POE
T
POD
T
AO
T
PAO
T
WLH
T
PLH
Parameter
I/O to output valid
I/O setup time before GCK
I/O hold time after GCK
GCK to output valid
Multiple FB internal operating
frequency
I/O setup time before p-term clock
input
I/O hold time after p-term clock input
P-term clock output valid
GTS to output valid
GTS to output disable
Product term OE to output enabled
Product term OE to output disabled
GSR to output valid
P-term S/R to output valid
GCK pulse width (High or Low)
P-term clock pulse width (High or Low)
Min
-
3.1
0
-
-
0.5
1.8
-
-
-
-
-
-
-
2.0
5.0
Max
4.0
-
-
2.0
250.0
-
-
4.6
2.5
2.5
5.5
5.5
7.7
8.5
-
-
XC95144XV-5
Min
-
3.7
0
-
-
0.7
2.0
-
-
-
-
-
-
-
2.2
5.0
Max
5.0
-
-
2.5
222.2
-
-
5.5
3.0
3.0
7.0
7.0
10.0
10.5
-
-
XC95144XV-7
Min
-
4.8
0
-
-
1.6
3.2
-
-
-
-
-
-
-
4.0
6.5
Max
7.5
-
-
4.5
125.0
-
-
7.7
5.0
5.0
9.5
9.5
12.0
12.6
-
-
Units
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Advance Information
Notes:
1.
Please contact Xilinx for up-to-date information on advance specifications.
4
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1-800-255-7778
DS051 (v2.0) January 25, 2001
Advance Product Specification
R
XC95144XV High-Performance CPLD
V
TEST
R
1
Device Output
R
2
C
L
Output Type
V
CCIO
3.3V
2.5V
1.8V
V
TEST
3.3V
2.5V
1.8V
R
1
320Ω
250Ω
10KΩ
R
2
360Ω
660Ω
14KΩ
C
L
35 pF
35 pF
35 pF
DS051_03_0601000
Figure 3:
AC Load Circuit
Internal Timing Parameters
XC95144XV-4
Symbol
Buffer Delays
T
IN
T
GCK
T
GSR
T
GTS
T
OUT
T
EN
T
PTCK
T
PTSR
T
PTTS
T
PDI
T
SUI
T
HI
T
ECSU
T
ECHO
T
COI
T
AOI
T
RAI
T
LOGI
T
LOGILP
T
F
T
PTA
T
PTA2
T
SLEW
Input buffer delay
GCK buffer delay
GSR buffer delay
GTS buffer delay
Output buffer delay
Output buffer enable/disable delay
Product term clock delay
Product term set/reset delay
Product term 3-state delay
Combinatorial logic propagation delay
Register setup time
Register hold time
Register clock enable setup time
Register clock enable hold time
Register clock to output valid time
Register async. S/R to output delay
Register async. S/R recover before clock
Internal logic delay
Internal low power logic delay
FastCONNECT II™ feedback delay
Incremental product term allocator delay
Adjacent macrocell p-term allocator delay
Slew-rate limited delay
-
-
-
-
-
-
-
-
-
-
1.3
1.0
1.3
1.0
-
-
4.0
-
-
-
-
-
-
0.8
3.8
1.7
0.6
0.2
2.5
1.2
0.2
1.2
2.5
1.6
0
1.6
0.8
4.3
0.4
-
-
-
-
0.2
4.9
-
-
-
-
-
-
-
-
-
-
1.5
1.2
1.5
1.2
-
-
5.0
-
-
-
-
-
-
1.0
5.0
1.8
0.7
0.3
3.0
1.5
0.3
2.0
3.0
2.0
0
1.8
1.0
5.5
0.5
-
-
-
-
0.2
6.0
-
-
-
-
-
-
-
-
-
-
2.6
2.2
2.6
2.2
-
-
7.5
-
-
-
-
-
-
1.4
6.4
3.5
0.8
0.3
4.0
2.3
1.5
3.1
5.0
2.5
0
2.4
1.4
7.2
1.3
-
-
-
-
0.5
6.4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min
Max
XC95144XV-5
Min
Max
XC95144XV-7
Min
Max
Units
Product Term Control Delays
Internal Register and Combinatorial Delays
Feedback Delays
Time Adders
Advance Information
Notes:
1.
Please contact Xilinx for up-to-date information on advance specifications.
DS051 (v2.0) January 25, 2001
Advance Product Specification
www.xilinx.com
1-800-255-7778
5
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