XC95144XV-5TQG100I datasheet, PDF

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XC95144XV-5TQG100I: DescriptionFlash PLD, 4ns, PQFP100, PLASTIC, TQFP-100; CategoryProgrammable logic devices Programmable logic; File Size80KB，9 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/; Environmental Compliance

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XC95144XV-5TQG100I Overview

Flash PLD, 4ns, PQFP100, PLASTIC, TQFP-100

XC95144XV-5TQG100I Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	XILINX
Parts packaging code	QFP
package instruction	PLASTIC, TQFP-100
Contacts	100
Reach Compliance Code	compliant
JESD-30 code	S-PQFP-G100
JESD-609 code	e3
length	14 mm
Humidity sensitivity level	3
Dedicated input times
Number of I/O lines	81
Number of terminals	100
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	0 DEDICATED INPUTS, 81 I/O
Output function	REGISTERED
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
Programmable logic type	FLASH PLD
propagation delay	4 ns
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage	2.6 V
Minimum supply voltage	2.4 V
Nominal supply voltage	2.5 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	14 mm

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XC95144XV High-Performance

CPLD

DS051 (v2.0) January 25, 2001

Advance Product Specification

Features

•

144 macrocells with 3,200 usable gates

Available in small footprint packages

- 100-pin TQFP (81 user I/O pins)

- 144-pin TQFP (117 user I/O pins)

- 144-pin CSP (117 user I/O pins)

Optimized for high-performance 2.5V systems

- Low power operation

- Multi-voltage operation

Advanced system features

- In-system programmable

- Two separate output banks

- Superior pin-locking and routability with

FastCONNECT II™ switch matrix

- Extra wide 54-input Function Blocks

- Up to 90 product-terms per macrocell with

individual product-term allocation

- Local clock inversion with three global and one

product-term clocks

- Individual output enable per output pin

- Input hysteresis on all user and boundary-scan pin

inputs

- Bus-hold ciruitry on all user pin inputs

- Full IEEE Standard 1149.1 boundary-scan (JTAG)

Fast concurrent programming

Slew rate control on individual outputs

Enhanced data security features

Excellent quality and reliability

- Endurance exceeding 10,000 program/erase

cycles

- 20 year data retention

- ESD protection exceeding 2,000V

Power Estimation

Power dissipation in CPLDs can vary substantially depend-

ing on the system frequency, design application and output

loading. To help reduce power dissipation, each macrocell

in a XC9500XV device may be configured for low-power

mode (from the default high-performance mode). In addi-

tion, unused product-terms and macrocells are automati-

cally deactivated by the software to further conserve power.

For a general estimate of I

, the following equation may be

used:

(mA) = MC

(0.5) + MC

(0.3) + MC(0.0045 mA/MHz) f

Where:

= Macrocells in high-performance (default) mode

= Macrocells in low-power mode

MC = Total number of macrocells used

f = Clock frequency (MHz)

This calculation is based on typical operating conditions

using a pattern of 16-bit up/down counters in each Function

Block with no output loading. The actual I

value varies

with the design application and should be verified during

normal system operation.

Figure 1

shows the above estimation in a graphical form.

200

200 MHz

•

150

Typical ICC (mA)

100

Hi g

for

120 MHz

Description

The XC95144XV is a 2.5V CPLD targeted for high-perfor-

mance, low-voltage applications in leading-edge communi-

cations and computing systems. It is comprised of eight

54V18 Function Blocks, providing 3,200 usable gates with

propagation delays of 4 ns.

120

160

200

Clock Frequency (MHz)

DS051_01_012501

Figure 1:

Typical I

vs. Frequency for XC95144XV

http://www.xilinx.com/legal.htm.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS051 (v2.0) January 25, 2001

Advance Product Specification

www.xilinx.com

1-800-255-7778

XC95144XV-5TQG100I Related Products

	XC95144XV-5TQG100I	XC95144XV-5CSG144I	XC95144XV-5TQG144I	XC95144XV-4TQG144I	XC95144XV-4TQG100I
Description	Flash PLD, 4ns, PQFP100, PLASTIC, TQFP-100	Flash PLD, 4ns, PBGA144, PLASTIC, CSP-144	Flash PLD, 4ns, PQFP144, PLASTIC, TQFP-144	Flash PLD, 4ns, PQFP144, PLASTIC, TQFP-144	Flash PLD, 4ns, PQFP100, PLASTIC, TQFP-100
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to
Maker	XILINX	XILINX	XILINX	XILINX	XILINX
Parts packaging code	QFP	BGA	QFP	QFP	QFP
package instruction	PLASTIC, TQFP-100	PLASTIC, CSP-144	PLASTIC, TQFP-144	PLASTIC, TQFP-144	PLASTIC, TQFP-100
Contacts	100	144	144	144	100
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant
JESD-30 code	S-PQFP-G100	S-PBGA-B144	S-PQFP-G144	S-PQFP-G144	S-PQFP-G100
JESD-609 code	e3	e1	e3	e3	e3
length	14 mm	12 mm	20 mm	20 mm	14 mm
Humidity sensitivity level	3	3	3	3	3
Number of I/O lines	81	117	117	117	81
Number of terminals	100	144	144	144	100
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
organize	0 DEDICATED INPUTS, 81 I/O	0 DEDICATED INPUTS, 117 I/O	0 DEDICATED INPUTS, 117 I/O	0 DEDICATED INPUTS, 117 I/O	0 DEDICATED INPUTS, 81 I/O
Output function	REGISTERED	REGISTERED	REGISTERED	REGISTERED	REGISTERED
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFQFP	TFBGA	LFQFP	LFQFP	LFQFP
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260	260	260	260	260
Programmable logic type	FLASH PLD	FLASH PLD	FLASH PLD	FLASH PLD	FLASH PLD
propagation delay	4 ns	4 ns	4 ns	4 ns	4 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.6 mm	1.2 mm	1.6 mm	1.6 mm	1.6 mm
Maximum supply voltage	2.6 V	2.6 V	2.6 V	2.6 V	2.6 V
Minimum supply voltage	2.4 V	2.4 V	2.4 V	2.4 V	2.4 V
Nominal supply voltage	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES	YES	YES
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	MATTE TIN	TIN SILVER COPPER	MATTE TIN	MATTE TIN	MATTE TIN
Terminal form	GULL WING	BALL	GULL WING	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.8 mm	0.5 mm	0.5 mm	0.5 mm
Terminal location	QUAD	BOTTOM	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	40	40	40	30	30
width	14 mm	12 mm	20 mm	20 mm	14 mm

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