HD74HC161RP-EL datasheet, PDF - EEWORLD Datasheet

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HD74HC161RP-EL: DescriptionHC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, FP-16DN; Categorylogic logic; File Size89KB，16 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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HD74HC161RP-EL Overview

HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, FP-16DN

HD74HC161RP-EL Parametric

Parameter Name	Attribute value
Maker	Renesas Electronics Corporation
Parts packaging code	SOIC
package instruction	SOP,
Contacts	16
Reach Compliance Code	compliant
Counting direction	UP
series	HC/UH
JESD-30 code	R-PDSO-G16
length	9.9 mm
Load/preset input	YES
Logic integrated circuit type	BINARY COUNTER
Operating mode	SYNCHRONOUS
Number of digits	4
Number of functions	1
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
propagation delay (tpd)	200 ns
Certification status	Not Qualified
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	6 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	4.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Trigger type	POSITIVE EDGE
width	3.95 mm

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HD74HC160/HD74HC161/

HD74HC162/HD74HC163

Synchronous Decade Counter (Direct Clear)

Synchronous 4-bit Binary Counter (Direct Clear)

Synchronous Decade Counter (Synchronous Clear)

Synchronous 4-bit Binary Counter (Synchronous Clear)

Description

The HD74HC160 and the HD74HC162 are 4 bit decade counters, and the HD74HC161 and the

HD74HC163 are 4 bit binary counters All flip-flops are clocked simultaneously on the low to high to

transition (positive edge) of the clock input waveform.

These counters may be preset using the load input. Presetting of all four flip-flops is synchronous to thte

rising edge of clock. When load is held low counting is disabled and the data on the A, B, C, and D inputs

is loaded into the counter on the rising edge of clock. If the load input is taken high before the positive

edge of clock the count operation will be unaffected.

All of these counters may be cleared by utilizing the clear input. The clear function on the HD74HC162

and HD74HC163 counters are synchronous to the clock. That is, the counters are cleared on the positive

edge of clock while the clear input is held low.

The HD74HC160 and HD74HC161 counters are cleared asynchronously. When the clear is taken low the

counter is cleared immediately regardless of the clock.

Two active high enable inputs Enable P and Enable T and a ripple carry output are provided to enable easy

cascading of counters. Both enable inputs must be high to count. The Enable T input also enables the

Ripple Carry output. When enabled, the Ripple Carry outputs a positive pulse when the counter overflows.

This pulse is approximately equal in duration to the high level portion of the Q

outputs. The Ripple Carry

output is fed to successive cascaded stages to facilitate easy implementation of N-bit counters.

Features

•

High Speed Operation: t

(Clock to Q) = 18 ns typ (C

= 50 pF)

High Output Current: Fanout of 10 LSTTL Loads

Wide Operating Voltage: V

= 2 to 6 V

Low Input Current: 1 µA max

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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