DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD70325
V25+
TM
16/8-BIT SINGLE-CHIP MICROCONTROLLER
The
µ
PD70325 (V25+) is a single-chip microcontroller on which 16-bit CPU, RAM, serial interface, timer, DMA
controller, interrupt controller, etc. are all integrated. The
µ
PD70325 is software compatible with the 16/8-bit single-
chip microcontroller
µ
PD70320 (V25
TM
). The V25+ greatly improves the DMA responsivity and transfer rate compared
to the V25.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
Software compatible with V25
Software compatible with
µ
PD70108/70116 (in native mode) (some instructions added)
Internal 16-bit architecture and external 8-bit data bus
3-stage pipeline method
Minimum instruction cycle : 250 ns/8 MHz (external 16 MHz)
: 200 ns/10 MHz (external 20 MHz)
Memory space 1 Mbyte
On-chip RAM : 256 words
×
8 bits
Register bank (memory mapped method) : 8 banks
Input port (port T) with comparator : 8 bits
I/O lines (input port : 4 bits, input/output ports : 20 bits)
Serial interface : 2 channels
• Internal dedicated baud rate generator
• Asynchronous mode and I/O interface mode
•
Interrupt controller
• Programmable priority (8 levels)
• 3 types of interrupt response method
Vectored interrupt function, register bank switching function, macro service function
•
•
DRAM and pseudo SRAM refreshing function
DMA controller : 2 channels
• 4 types of DMA transfer mode
• Transfer rate
Maximum 4 Mbytes/second (when stop control is not executed by DMARQ pin in demand release
mode)
Maximum 2 Mbytes/second (when stop control is executed by DMARQ pin in demand release
mode, or burst mode)
• Address pointer (linear) : 20 bits
• Terminal counter : 16 bits
•
•
•
•
•
16-bit timer : 2 channels
Time base counter (20 bits) : 1 channel
On-chip clock generator
Programmable wait function
Standby function (STOP, HALT)
The information in this document is subject to change without notice.
Document No. U12850EJ7V0DS00 (7th edition)
Date Published November 1997 N
Printed in Japan
The mark
shows major revised points.
©
1996
1995
µ
PD70325
Comparison between V25 and V25+
V25
V35
TM
V25+
V35+
TM
µ
PD70320
Transfer processing method
Maximum transfer rate (8-MHz
operation)
Sampling timing of DMA request
DMA service channel
µ
PD70330
µ
PD70325
µ
PD70335
Depends on microprogram
0.6 Mbytes/second 0.8 Mbytes/second
Depends on dedicated hardware
4 Mbytes/second
5.3 Mbytes/second
Between instruction execution cycles
In on-chip RAM area
Between bus cycles
In special function register
Linear method
1 DMA transfer/1 bus cycle
Not accepted
Specification method of transfer address Segment method
Execution format in single-step mode 1 DMA transfer/1 instruction execution
DMA
Interrupt request during DMA transfer Accepts only NMI
function (demand release mode)
Number of necessary waits when
stop is controlled by DMARQ
(demand release mode)
Transfer processing units
TC (terminal counter) setting value
Not necessary
2 waits
Byte/word
Byte/word
Byte
Byte/word
Number of times of DMA transfer
(Number of times of DMA transfer) – 1
TC = FFFFH
Expanded by wait insertion
Available (SCK0 pin)
Generation timing of terminal counter TC = 0
TC output low-level width
Transmit clock output in
asynchronous mode (channel 0)
Serial error register
Serial
interface Receive buffer full flag
Transmit buffer empty flag
All sent flag
Interrupt
Interrupt source register
function
External data bus
Maximum operating frequency
Yes
No
No
No
No
8 bits
8 MHz
16 bits
Fixed
Not available
Serial status register
In serial status register
In serial status register
In serial status register
Yes
8 bits
10 MHz
16 bits
3
µ
PD70325
PIN CONFIGURATION (Top View)
94-Pin Plastic QFP
µ
PD70325GJ-8-5BG
µ
PD70325GJ-10-5BG
P07/CLKOUT
A11
A10
94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72
71
A12
NC
A13
A14
A15
A16
A17
A18
A19
RxD0
GND
CTS0
TxD0
RxD1
CTS1
TxD1
P20/DMARQ0
IC
V
DD
V
DD
P21/DMAAK0
NC
P22/TC0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
P05
NC
IC
P04
P03
P02
P01
P00
EA
MREQ
IOSTB
MSTB
R/W
REFRQ
RESET
V
DD
V
DD
X2
X1
GND
GND
NC
NC
V
TH
P13/INTP2/INTAK
P14/INT/POLL
P23/DMARQ1
P24/DMAAK1
P27/HLDRQ
P11/INTP0
P26/HLDAK
P12/INTP1
P15/TOUT
P25/TC1
NMI (P10)
P16/SCK0
P17/READY
IC
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
Remarks 1.
NC : Non-Connection
2.
IC : Internally Connected
Cautions 1. Fix IC pin individually to high level via a pull-up resistor externally.
2. Fix EA pin to low level.
4
NC
IC
P06
NC
D7
D6
D5
D4
D3
D2
D1
D0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
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