FemtoClock® NG Crystal-to-LVDS
Clock Synthesizer
844N255I
Data Sheet
General Description
The 844N255I is a 6-output clock synthesizer designed for wireless
infrastructure clock applications. The device uses IDT’s fourth
generation FemtoClock® NG technology for an optimum of high
clock frequency and low phase noise performance, combined with a
low power consumption and high power supply noise rejection. The
reference frequency is selectable and the following frequency is
supported: 25MHz. The synthesizer generates selectable
156.25MHz, 125MHz, 100MHz, 50MHz and 25MHz clock signals.
The device is optimized for very low phase noise and cycle to cycle
jitter. The synthesized clock frequency and the phase-noise
performance are optimized for driving SRIO 1.3 and 2.0 SerDes
reference, DSP and host-processor clocks. The device supports a
2.5V voltage supply and is packaged in a small, lead-free (RoHS 6)
48-lead VFQFN package. The extended temperature range supports
wireless infrastructure, telecommunication and networking end
equipment requirements.
Features
•
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4
TH
generation FemtoClock® NG technology
Selectable 156.25MHz, 125MHz, 100MHz, 50MHz and 25MHz
output clock signals synthesized from a 25MHz reference
frequency
Six differential LVDS clock outputs
Crystal interface designed for a 25MHz crystal
RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1MHz - 20MHz): 0.27ps (typical)
Internal regulator for optimum noise rejection
LVCMOS interface levels for the frequency select and output
enable inputs
Full 2.5V supply voltage
Lead-free (RoHS 6) 48-lead VFQFN package
-40°C to 85°C ambient operating temperature
Block Diagram
XTAL_IN
25MHz
XTAL_OUT
25MHz
OSC
0
PFD
&
1
FemtoClock® NG
VCO
÷M
÷16
÷20,
÷25
÷20,
÷25
÷50,
÷100
÷50
÷100
QA
nQA
QB0
nQB0
QB1
nQB1
QC
nQC
Pulldown
Pulldown
REF_CLK
Pulldown
REF_SEL
MSEL
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Pulldown
FSELB
FSELC
FSELD
Pulldown
Pulldown
Pulldown
5
QD
©2016 Integrated Device Technology, Inc
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April 28, 2016
844N255I Data Sheet
Pin Assignment
XTAL_OUT
REF_CLK
REF_SEL
XTAL_IN
MSEL
GND
GND
GND
38
48
47
46
45
44
43
42
41
40
39
37
36
GND
35
VDDA
34
VDD
33
nOEE
GND
1
VDDOA
2
QA
3
nQA
4
GNDA
5
nOEA
6
nOEB
7
VDDOB
8
QB0
9
nQB0
10
QB1
11
nQB1
12
13
14
15
16
17
18
19
20
21
22
23
24
GND
32
VDDOE
31
QE
30
nQE
29
GNDE
28
FSELE
27
VDDOD
26
QD
25
nQD
VDD
VDD
FSELC
844N255I
48-lead VFQFN
7.0mm x 7.0mm x 0.925mm, package body
K Package, Top View
FSELB
GNDB
nOEC
VDD
FSELD
VDDOC
GNDC
nOED
VDD
QC
nQC
©2016 Integrated Device Technology, Inc
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April 28, 2016
844N255I Data Sheet
Table 1. Pin Descriptions
Number
1, 36, 37, 38, 39, 48
2
3, 4
5
6
7
8
9, 10,
11, 12
13
14
15
16, 17
18
19
20
21, 34, 40, 41, 43
22
23
24
25, 26
27
28
29
30, 31
32
33
35
42
44,
45
46
47
Name
GND
V
DDOA
QA, nQA
GNDA
nOEA
nOEB
V
DDOB
QB0, nQB0,
QB1, nQB1
GNDB
FSELB
GNDC
QC, nQC
V
DDOC
nOEC
FSELC
V
DD
FSELD
nOED
GNDD
nQD, QD
V
DDOD
FSELE
GNDE
nQE, QE
V
DDOE
nOEE
V
DDA
MSEL
XTAL_IN,
XTAL_OUT
REF_SEL
REF_CLK
Power
Power
Output
Power
Input
Input
Power
Output
Power
Input
Power
Output
Power
Input
Input
Power
Input
Input
Power
Output
Power
Input
Power
Output
Power
Input
Power
Input
Input
Input
Input
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
Pulldown
Pulldown
Pulldown
Pullup
Pulldown
Pulldown
Pulldown
Type
Description
Power supply ground.
Output supply pin for the output QA.
Differential clock output A. LVDS interface levels.
Power supply ground for the output QA.
Output enable input. See Table 3G. LVCMOS/LVTTL interface levels.
Output enable input. See Table 3H. LVCMOS/LVTTL interface levels.
Output supply pin for the Bank QB outputs.
Differential clock outputs (Bank B). LVDS interface levels.
Power supply ground for the outputs QB0 and QB1.
Frequency select input for Bank B outputs. See Table 3C.
LVCMOS/LVTTL interface levels.
Power supply ground for the output QC.
Differential clock output C. LVDS interface levels.
Output supply pin for the output QC.
Output enable input. See Table 3I. LVCMOS/LVTTL interface levels.
Frequency select input for output QC. See Table 3D.
LVCMOS/LVTTL interface levels.
Core supply pin.
Frequency select input for output QD. See Table 3E.
LVCMOS/LVTTL interface levels.
Output enable input. See Table 3J. LVCMOS/LVTTL interface levels.
Power supply ground for the output QD.
Differential clock output D. LVDS interface levels.
Output supply pin for the output QD.
Frequency select input for output QE. See Table 3F.
LVCMOS/LVTTL interface levels.
Power supply ground for the output QE.
Differential clock output E. LVDS interface levels.
Output supply pin for the output QE.
Output enable input. See Table 3K. LVCMOS/LVTTL interface levels.
Analog power supply.
Unused control input. Connect to logic LOW level. See Table 3A.
LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the
output.
Reference select input. See Table 3B for function.
LVCMOS/LVTTL interface levels.
Alternative reference clock input. See Table 3B.
LVCMOS/LVTTL interface levels.
NOTE:
Pulldown and Pullup
refer to an internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
©2016 Integrated Device Technology, Inc
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844N255I Data Sheet
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
3.5
51
51
Maximum
Units
pF
k
k
Function Tables
Table 3A. Input Reference Frequency and PLL Feedback Multiplier
Reference Frequency Select
MSEL
0 (default)
Reference Frequency
f
ref
25MHz
PLL Feedback Multiplier M
100
Table 3B. PLL Reference Clock Select Function Table
Input
REF_SEL
0 (default)
1
Operation
The crystal interface is selected as reference clock. Crystal frequency is 25MHz.
The external reference input REF_CLK is selected.
NOTE: REF_SEL is an asynchronous control.
Table 3C.
Output QB
[1:0]
Frequency Select Function Table
Input
FSELB
0 (default)
1
QB[1:0], nQB[1:0] Frequency (MHz)
125
100
NOTE: FSELB is an asynchronous control.
Table 3D.
Output QC Frequency Select Function Table
Input
FSELC
0
1 (default)
125
100
QC, nQC Frequency (MHz)
NOTE: FSELC is an asynchronous control.
Table 3E. Output QD Frequency Select Function Table
Input
FSELD
0 (default)
1
NOTE: FSELD is an asynchronous control.
50
25
QD, nQD Frequency (MHz)
©2016 Integrated Device Technology, Inc
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April 28, 2016
844N255I Data Sheet
Table 3F. Output QE Frequency Select Function Table
Input
FSELE
0
1 (default)
50
25
QE, nQE Frequency (MHz)
NOTE 1: FSELE is an asynchronous control.
Table 3G. nOEA Output Enable Function Table
Input
nOEA
0 (default)
1
Output enabled
Output disabled in high-impedance state
QA, nQA Frequency (MHz)
NOTE: nOEA is an asynchronous control.
Table 3H. nOEB Output Enable Function Table
Input
nOEB
0 (default)
1
QB0, nQB0 - QB1, nQB1 outputs are enabled
QB0, nQB0 - QB1, nQB1 Outputs are disabled (high-impedance)
Operation
NOTE: nOEB is an asynchronous control.
Table 3I. nOEC Output Enable Function Table
Input
nOEC
0 (default)
1
QC, nQC output is enabled
QC, nQC output is disabled (high-impedance)
Operation
NOTE: nOEC is an asynchronous control.
Table 3J. nOED Output Enable Function Table
Input
nOED
0 (default)
1
QD, nQD output is enabled
QD, nQD output is disabled (high-impedance)
Operation
NOTE: nOED is an asynchronous control.
Table 3K. nOEE Output Enable Function Table
Input
nOEE
0 (default)
1
QE, nQE output is enabled
QE, nQE is disabled (high-impedance)
Operation
NOTE 1: nOEE is an asynchronous control.
©2016 Integrated Device Technology, Inc
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April 28, 2016
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