QL3040-3PQ208M datasheet, PDF - EEWORLD Datasheet

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QL3040-3PQ208M: DescriptionField Programmable Gate Array, 1008 CLBs, 40000 Gates, 1008-Cell, CMOS, PQFP208, 28 X 28 MM, 3.35 MM HEIGHT, PLASTIC, MS-029, QFP-208; CategoryProgrammable logic devices Programmable logic; File Size208KB，19 Pages; ManufacturerQuickLogic Corporation; Websitehttps://www.quicklogic.com

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QL3040-3PQ208M Overview

Field Programmable Gate Array, 1008 CLBs, 40000 Gates, 1008-Cell, CMOS, PQFP208, 28 X 28 MM, 3.35 MM HEIGHT, PLASTIC, MS-029, QFP-208

QL3040-3PQ208M Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	QuickLogic Corporation
Parts packaging code	QFP
package instruction	28 X 28 MM, 3.35 MM HEIGHT, PLASTIC, MS-029, QFP-208
Contacts	208
Reach Compliance Code	compliant
ECCN code	3A001.A.2.C
JESD-30 code	S-PQFP-G208
JESD-609 code	e0
length	28 mm
Humidity sensitivity level	3
Configurable number of logic blocks	1008
Equivalent number of gates	40000
Number of entries	252
Number of logical units	1008
Output times	244
Number of terminals	208
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	1008 CLBS, 40000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	FQFP
Encapsulate equivalent code	QFP208,1.2SQ,20
Package shape	SQUARE
Package form	FLATPACK, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3,3.3/5 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	4.1 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	28 mm

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QL3040 pASIC 3 FPGA Data Sheet

••••••

40,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance

and High Density

Device Highlights

High Performance & High Density

•

40,000 Usable PLD Gates with 252 I/Os

•

300 MHz 16-bit Counters,

Eight Low-Skew Distributed

Networks

•

Two array clock/control networks available

400 MHz Datapaths

•

0.35

µm

four-layer metal non-volatile

CMOS process for smallest die sizes

Easy to Use / Fast Development

Cycles

•

100% routable with 100% utilization and

to the logic cell flip-flop clock, set and reset

inputs — each driven by an input-only pin

•

Six global clock/control networks available

to the logic cell; F1, clock set, reset inputs

and the input, I/O register clock, reset, and

enable inputs as well as the output enable

control — each driven by an input-only or

I/O pin, or any logic cell output or I/O cell

feedback

complete pin-out stability

•

Variable-grain logic cells provide high

performance and 100% utilization

•

Comprehensive design tools include high

quality Verilog/VHDL synthesis

High Performance

•

Input + logic cell + output total delays

under 6 ns

•

Data path speeds over 400 MHz

•

Counter speeds over 300 MHz

Advanced I/O Capabilities

•

Interfaces with both 3.3 V and 5.0 V devices

•

PCI compliant with 3.3 V and 5.0 V buses

for -1/-2/-3/-4 speed grades

•

Full JTAG boundary scan

•

I/O Cells with individually controlled

Registered Input Path and Output Enables

Total of 252 I/O Pins

•

244 bidirectional input/output pins,

PCI-compliant for 5.0 V and 3.3 V buses for

-1/-2/-3/-4 speed grades

•

Eight high-drive input/distributed

network pins

Figure 1: 1,008 pASIC 3 Logic Cells

www.quicklogic.com

•

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