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Mobile Intel
®
Celeron
®
Processor (0.13 µ) in
Micro-FCBGA and Micro-FCPGA Packages
at 1.33 GHz, 1.20 GHz, 1.13 GHz, 1.06 GHz,
1.00 GHz; Low Voltage 866 MHz, 733 MHz, 650
MHz; and Ultra Low Voltage 800 MHz, 733 MHz,
700 MHz, and 650 MHz
Datasheet
January 2003
Order Number: 298517-005
Introduction
R
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended
for use in medical, life saving, or life sustaining applications.
The information provided in this report, and related materials and presentations, are intended to illustrate the effects of certain design variables
as determined by modeling, and are neither a recommendation nor endorsement of any specific system-level design practices or targets. The
model results are based on a simulated notebook configuration, and do not describe or characterize the properties of any specific, existing
system design. A detailed description of the simulated notebook configuration is available upon request.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future
definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Mobile Intel Celeron Processor may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:
Intel Corporation
www.intel.com
or call 1-800-548-4725
Intel, Intel logo, Celeron, Pentium, and MMX are registered trademarks or trademarks of Intel Corporation and its subsidiaries in the United States and
other countries.
*Other names and brands may be claimed as the property of others.
Copyright © Intel Corporation 2000-2002
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Mobile Intel
®
Celeron
®
Processor (0.13 µ) in
Micro-FCBGA and Micro-FCPGA Packages Datasheet
Introduction
R
Contents
1.
Introduction .................................................................................................................................10
1.1
1.2
1.3
1.4
2.
2.1
Overview ........................................................................................................................10
State of the Data ............................................................................................................11
Terminology ...................................................................................................................11
References.....................................................................................................................12
New Features in the Mobile Intel Celeron Processor ....................................................13
2.1.1 133-MHz PSB With AGTL Signaling ...................................................................13
2.1.2 256-K On-die Integrated L2 Cache .....................................................................13
2.1.3 Data Prefetch Logic .............................................................................................13
2.1.4 Differential Clocking.............................................................................................13
2.1.5 Signal Differences Between the Mobile Intel Celeron Processor (0.18 µ) (in
BGA2 and Micro-PGA2 Packages) and the Mobile Intel Celeron Processor
(0.13 µ) (in Micro-FCBGA and Micro-FCPGA Packages)...................................14
Power Management.......................................................................................................14
2.2.1 Clock Control Architecture...................................................................................14
2.2.2 Normal State........................................................................................................14
2.2.3 Auto Halt State ....................................................................................................14
2.2.4 Quick Start State .................................................................................................15
2.2.5 HALT/Grant Snoop State ....................................................................................16
2.2.6 Deep Sleep State ................................................................................................16
2.2.7 Operating System Implications of Low-power States..........................................17
AGTL Signals.................................................................................................................17
Mobile Intel Celeron Processor CPUID .........................................................................17
Processor System Signals .............................................................................................19
3.1.1 Power Sequencing Requirements.......................................................................20
3.1.2 Test Access Port (TAP) Connection....................................................................20
3.1.3 Catastrophic Thermal Protection.........................................................................21
3.1.4 Unused Signals ...................................................................................................21
3.1.5 Signal State in Low-power States .......................................................................21
3.1.5.1
System Bus Signals ........................................................................21
3.1.5.2
CMOS and Open-drain Signals ......................................................21
3.1.5.3
Other Signals ..................................................................................22
Power Supply Requirements .........................................................................................22
3.2.1 Decoupling Guidelines ........................................................................................22
3.2.2 Voltage Planes ....................................................................................................22
3.2.3 Voltage Identification ...........................................................................................23
3.2.4 VTTPWRGD Signal Quality Specification ...........................................................24
3.2.4.1
Transition Region ............................................................................24
3.2.4.2
Transition Time ...............................................................................24
3.2.4.3
Noise ...............................................................................................25
System Bus Clock and Processor Clocking...................................................................25
Maximum Ratings ..........................................................................................................26
DC Specifications...........................................................................................................26
Mobile Intel Celeron Processor Features ...................................................................................13
2.2
2.3
2.4
3.
3.1
Electrical Specifications..............................................................................................................19
3.2
3.3
3.4
3.5
Mobile Intel
®
Celeron
®
Processor (0.13 µ) in
Micro-FCBGA and Micro-FCPGA Packages Datasheet
3
Introduction
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3.6
4.
AC Specifications .......................................................................................................... 40
3.6.1 System Bus, Clock, APIC, TAP, CMOS, and Open-drain AC Specifications..... 40
System Bus Clock (BCLK) and PICCLK DC Specifications and AC Signal Quality
Specifications ................................................................................................................ 40
AGTL AC Signal Quality Specifications ........................................................................ 40
Non-AGTL Signal Quality Specifications....................................................................... 40
4.3.1 PWRGOOD, VTTPWRGD Signal Quality Specifications ................................... 40
4.3.1.1
VTTPWRGD Noise Parameter Specification ................................. 40
4.3.1.2
VTTPWRGD Transition Parameter Recommendation ................... 40
4.3.1.2.1
Transition Region ......................................................... 40
4.3.1.2.2
Transition Time............................................................. 40
4.3.1.2.3
Noise............................................................................. 40
Socketable Micro-FCPGA Package .............................................................................. 40
Surface Mount Micro-FCBGA Package ........................................................................ 40
Signal Listings ............................................................................................................... 40
Thermal Diode ............................................................................................................... 40
Description..................................................................................................................... 40
7.1.1 Quick Start Enable .............................................................................................. 40
7.1.2 System Bus Frequency....................................................................................... 40
7.1.3 APIC Enable........................................................................................................ 40
Clock Frequencies and Ratios ...................................................................................... 40
Alphabetical Signal Reference ...................................................................................... 40
Signal Summaries ......................................................................................................... 40
Introduction................................................................................................................... 40
Filter Specification ........................................................................................................ 40
Recommendation for Mobile Systems ......................................................................... 40
Comments .................................................................................................................... 40
System Signal Simulations......................................................................................................... 40
4.1
4.2
4.3
5.
Mechanical Specifications.......................................................................................................... 40
5.1
5.2
5.3
6.
7.
V
CC
Thermal Specifications ........................................................................................................ 40
6.1
7.1
Processor Initialization and Configuration.................................................................................. 40
7.2
8.
8.1
8.2
A1.
A2.
A3.
A4.
Processor Interface .................................................................................................................... 40
Appendix A. PLL RLC Filter Specification ......................................................................................................... 40
4
Mobile Intel
®
Celeron
®
Processor (0.13 µ) in
Micro-FCBGA and Micro-FCPGA Packages Datasheet
Introduction
R
Figures
Figure 1. Clock Control States................................................................................................. 15
Figure 2. PLL RLC Filter.......................................................................................................... 23
Figure 3. VTTPWRGD System-Level Connections................................................................. 24
Figure 4. Noise Estimation ...................................................................................................... 25
Figure 5. Illustration of V
CC
Static and Transient Tolerances (VID = 1.15 V) ......................... 37
Figure 6. Illustration of Deep Sleep V
CC
Static and Transient Tolerances (VID
Setting = 1.15 V) ...................................................................................................... 37
Figure 7. Illustration of V
CC
Static and Transient Tolerances (VID = 1.40 V) ......................... 38
Figure 8. Illustration of Deep Sleep V
CC
Static and Transient Tolerances (VID
Setting = 1.40 V) ...................................................................................................... 39
Figure 9. BCLK (Single Ended)/PICCLK/TCK Generic Clock Timing Waveform.................... 40
Figure 10. Differential BCLK/BCLK# Waveform (Common Mode).......................................... 40
Figure 11. BCLK/BCLK# Waveform (Differential Mode) ......................................................... 40
Figure 12. Valid Delay Timings................................................................................................ 40
Figure 13. Setup and Hold Timings ......................................................................................... 40
Figure 14. Cold/Warm Reset and Configuration Timings........................................................ 40
Figure 15. Power-on Sequence and Reset Timings................................................................ 40
Figure 16. Power Down Sequencing and Timings (VCC Leading) ......................................... 40
Figure 17.Power Down Sequencing and Timings (V
CCT
Leading)........................................... 40
Figure 18.Test Timings (Boundary Scan)................................................................................ 40
Figure 19. Test Reset Timings ................................................................................................ 40
Figure 20.Quick Start/Deep Sleep Timing (BCLK Stopping Method)...................................... 40
Figure 21. Quick Start/Deep Sleep Timing (DPSLP# Assertion Method) ............................... 40
Figure 22. BCLK (Single Ended)/PICCLK Generic Clock Waveform...................................... 40
Figure 23. Maximum Acceptable Overshoot/Undershoot Waveform ...................................... 40
Figure 24. VTTPWRGD Noise Specification ........................................................................... 40
Figure 25. Socketable Micro-FCPGA Package - Top and Bottom Isometric Views................ 40
Figure 26. Socketable Micro-FCPGA Package - Top and Side View ..................................... 40
Figure 27. Socketable Micro-FCPGA Package - Bottom View ............................................... 40
Figure 28. Micro-FCBGA Package – Top and Bottom Isometric Views.................................. 40
Figure 29. Micro-FCBGA Package – Top and Side Views...................................................... 40
Figure 30. Micro-FCBGA Package - Bottom View .................................................................. 40
Figure 31. Pin/Ball Map - Top View ......................................................................................... 40
Figure 32. PLL Filter Specifications......................................................................................... 40
Mobile Intel
®
Celeron
®
Processor (0.13 µ) in
Micro-FCBGA and Micro-FCPGA Packages Datasheet
5
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