CY7C1524KV18-333BZXI datasheet, PDF

Datasheet> All Categories > storage> storage> CY7C1524KV18-333BZXI

CY7C1524KV18-333BZXI: DescriptionDDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 13 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165; Categorystorage storage; File Size883KB，32 Pages; ManufacturerCypress Semiconductor; Environmental Compliance

Download Datasheet Parametric View All

CY7C1524KV18-333BZXI Overview

DDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 13 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165

CY7C1524KV18-333BZXI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Cypress Semiconductor
Parts packaging code	BGA
package instruction	15 X 13 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	333 MHz
I/O type	SEPARATE
JESD-30 code	R-PBGA-B165
length	15 mm
memory density	75497472 bit
Memory IC Type	DDR SRAM
memory width	36
Number of functions	1
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2MX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
power supply	1.5/1.8,1.8 V
Certification status	Not Qualified
Maximum seat height	1.4 mm
Minimum standby current	1.7 V
Maximum slew rate	0.64 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	13 mm

Preview

Download Datasheet

View All

CY7C1522KV18, CY7C1529KV18

CY7C1523KV18, CY7C1524KV18

72-Mbit DDR II SIO SRAM 2-Word

Burst Architecture

Features

■

Functional Description

The CY7C1522KV18, CY7C1529KV18, CY7C1523KV18, and

CY7C1524KV18 are 1.8V Synchronous Pipelined SRAMs,

equipped with DDR II SIO (Double Data Rate Separate I/O)

architecture. The DDR II SIO consists of two separate ports: the

read port and the write port to access the memory array. The

read port has data outputs to support read operations and the

write port has data inputs to support write operations. The DDR

II SIO has separate data inputs and data outputs to completely

eliminate the need to “turnaround” the data bus required with

common I/O devices. Access to each port is accomplished

through a common address bus. Addresses for read and write

are latched on alternate rising edges of the input (K) clock. Write

data is registered on the rising edges of both K and K. Read data

is driven on the rising edges of C and C if provided, or on the

rising edge of K and K if C/C are not provided. Each address

location is associated with two 8-bit words in the case of

CY7C1522KV18, two 9-bit words in the case of

CY7C1529KV18, two 18-bit words in the case of

CY7C1523KV18, and two 36-bit words in the case of

CY7C1524KV18 that burst sequentially into or out of the device.

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs are tightly matched to the

two output echo clocks CQ/CQ, eliminating the need to capture

data separately from each individual DDR II SIO SRAM in the

system design. Output data clocks (C/C) enable maximum

system clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

72 Mbit Density (8M x 8, 8M x 9, 4M x 18, 2M x 36)

333 MHz Clock for High Bandwidth

2-word Burst for reducing Address Bus Frequency

Double Data Rate (DDR) Interfaces

(data transferred at 666 MHz) at 333 MHz

Two Input Clocks (K and K) for precise DDR Timing

❐

SRAM uses rising edges only

Two Input Clocks for Output Data (C and C) to minimize Clock

Skew and Flight Time mismatches

Echo Clocks (CQ and CQ) simplify Data Capture in High Speed

Systems

Synchronous Internally Self timed Writes

DDR II operates with 1.5 Cycle Read Latency when DOFF is

asserted HIGH

Operates similar to DDR-I Device with 1 Cycle Read Latency

when DOFF is asserted LOW

1.8V Core Power Supply with HSTL Inputs and Outputs

Variable Drive HSTL Output Buffers

Expanded HSTL Output Voltage (1.4V–V

)

❐

Supports both 1.5V and 1.8V IO supply

Available in 165-ball FBGA Package (13 x 15 x 1.4 mm)

Offered in both Pb-free and non Pb-free Packages

JTAG 1149.1 compatible Test Access Port

Phase Locked Loop (PLL) for accurate Data Placement

■

Configurations

CY7C1522KV18 – 8M x 8

CY7C1529KV18 – 8M x 9

CY7C1523KV18 – 4M x 18

CY7C1524KV18 – 2M x 36

Table 1. Selection Guide

Description

Maximum Operating Frequency

Maximum Operating Current

x18

x36

333 MHz

333

510

520

640

300 MHz

300

480

490

600

250 MHz

250

420

430

530

200 MHz

200

370

380

450

167 MHz

167

340

400

Unit

MHz

Cypress Semiconductor Corporation

Document Number: 001-00438 Rev. *F

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised January 29, 2010

[+] Feedback

Recommended Resources

How ALA circuit works

The most basic triode switching circuit

STK078-105 audio IC circuit diagram

NCP1014/1028 driver LED circuit

Output positive and negative polarity conversion circuit diagram

High voltage-low voltage conversion circuit diagram

Advantages and disadvantages of 7nm processors: Some time ago, AMD announced 7-nm Epyc x86 CPUs and Vega GPUs, bringing a new wave of hope to the industry that these chips will reduce the cost of high-end processors. The news also provided an examp...; 朗锐智科 Embedded System

I want a manufacturer to produce a PCB. What information should I submit to the manufacturer?: Does anyone know the specific process? In addition to preparing the circuit, is there anything else I need to give to the manufacturer in advance? I am a beginner, so please give me some advice!...; il739 PCB Design

Why is my account still waiting for member verification?: Why is my account still waiting for member verification? Why can’t I reply to other people’s posts? . . . . . . . ....; 369000753 Suggestions & Announcements

Gain indicator problem: The system design requires the amplifier gain to be 1.0-10 and the gain linearity to be no less than 1%. What I don’t understand is how to test the data to show that the linearity is no less than 1%? ...; wuli1314 Analog electronics

Keyboard filter driver implements shortcut keys: I want to write a keyboard filter driver to implement the function of shortcut keys, such as pressing F12 to open My Computer. Now the problem is that I can intercept the event of pressing F12, but ho...; bg3oje Embedded System

Yuan Fang, what do you think of this circuit? (1): Di: Yuan Fang, what do you think of this waveform?[align=left]Yuan Fang: Sir, this waveform is smooth and round, it looks like a good sine signal! [/align][align=left]Di: Well, if it is a sine signal,...; zjd01 Analogue and Mixed Signal

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components