iC-HC
ULTRA FAST DUAL HV-KOMPARATOR
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APPLICATIONS
o
Receiver for 24 V control
systems
o
A/D and D/A converters
o
Signal conditioning
o
Zero-crossing detectors
o
I/Os, level shift
o
Timing critical measurement
equipment
o
Time-to-digital converter
interfaces (TDC)
FEATURES
o
o
o
o
o
o
o
o
o
o
o
o
Independent input supply voltage range up to 36 V
Input voltage range down to VN
Differential input voltage of 36 V max.
Separate digital supply
Programmable hysteresis resp. hold function
Propagation delay typ. 5 ns
Power save mode with propagation delay of typ. 20 ns
Low current consumption stand-by mode
TTL and CMOS compatible logic inputs and outputs
8 mA CMOS outputs
Digital supply 3 to 5.5 V
All pins protected against ESD
PACKAGES
TSSOP16
BLOCK DIAGRAM
IN0
1
-
+
16
O0
IP0
2
15
NFAST
VP
3
14
VDD
T0
4
HYS
HOLD
13
P0
T1
5
12
P1
VN
6
Slow
Fast
11
GND
IP1
7
+
10
NEN
IN1
8
-
9
O1
Copyright © 2013 iC-Haus
http://www.ichaus.com
iC-HC
ULTRA FAST DUAL HV-KOMPARATOR
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DESCRIPTION
iC-HC features separate supply voltages for both the
analogue inputs and the logic outputs. The logic
power supply though must stay inside the boundaries
of the inputs power supply.
The iC also features a zero current consumption
standby mode as well as a current saving mode,
the latter reducing the current consumption by 80%,
though tripling the propagation delay.
Four values of input hysteresis (17 to 100 mV) or al-
ternatively a hold function can be configured. The
hold function blocks the toggling of the output for the
configured hold time. For hold times > 100 µs exter-
nal R/C networks can be used. Both hysteresis and
hold function can be deactivated.
PACKAGING INFORMATION TSSOP16 to JEDEC
PIN CONFIGURATION TSSOP16
PIN FUNCTIONS
No. Name Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
IN0
IP0
VP
T0
T1
VN
IP1
IN1
O1
NEN
GND
P1
P0
VDD
NFAST
O0
Neg. Input Comparator 0
Pos. Input Comparator 0
Pos. Power Supply
Configuration Input / ext. RC
Configuration input / ext. RC
Neg. Power Supply
Pos. Input Comparator 1
Neg. Input Comparator 1
Output Comparator 1
Standby (NEN = hi)
Logic Ground
Configuration Input
Configuration Input
Logic Power Supply 5/3.3 V
Power Save (NFAST = hi)
Output Comparator 0
IN0
1
-
+
16
O0
IP0
2
15
NFAST
VP
3
14
VDD
T0
4
HYS
HOLD
13
P0
T1
5
12
P1
VN
6
Slow
Fast
11
GND
IP1
7
+
10
NEN
IN1
8
-
9
O1
iC-HC
ULTRA FAST DUAL HV-KOMPARATOR
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Rev A1, Page 3/10
ABSOLUTE MAXIMUM RATINGS
Beyond these values damage may occur; device operation is not guaranteed.
Item
No.
Symbol
Parameter
Pos. Supply Voltage
Current in VP
V(IPx), V(INx)
I(IPx), I(INx)
Voltage at VDD
Logic Supply VDD
Current in VDD
Current in VDD
Voltage at GND
Current in GND
Voltage at output O0 and O1
Current in output O0 and O1
Current in iutput O0 and O1
V(NFAST,NEN,T0,T1,P0,P1)
I(NFAST,NEN,T0,T1,P0,P1)
Susceptibility to ESD at all pins
Storage Temperature Range
Chip Temperature
HBM, 100 pF discharged through 1.5 kΩ
-40
-40
referenced to VN
referenced to GND
referenced to GND
referenced to VN
referenced to VN
referenced to VN
referenced to GND
referenced to GND
referenced to VN
referenced to GND
Conditions
Min.
-0.5
-5
-2
-0.5
-0.5
-5
-5
-0.5
-5
-0.5
-20
-5
-0.5
-5
Max.
46
5
+2
46
6
20
5
46
5
6
+20
+5
6
+5
3
150
150
V
mA
V
mA
V
V
mA
mA
V
mA
V
mA
mA
V
mA
kV
°C
°C
Unit
G001 VP
G002 I(VP)
G003 V()
G004 I()
G005 VDD
G006 VDD
G007 I(VDD)
G008 I(VDD)
G009 GND
G010 I(GND)
G011 V()
G012 I()
G013 I()
G014 V()
G015 I()
G016 Vd()
G017 Ts
G018 Tj
VN
−
0.5 VP + 0.5
THERMAL DATA
Item
No.
T01
T02
Symbol
Ta
Rthja
Parameter
Operating Ambient Temperature Range
Thermal Resistance Chip/Ambient
Conditions
Min.
-40
Typ.
Max.
125
140
°C
K/W
Unit
All voltages are referenced to ground unless otherwise stated.
All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative.
iC-HC
ULTRA FAST DUAL HV-KOMPARATOR
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Rev A1, Page 4/10
ELECTRICAL CHARACTERISTICS
Item
No.
001
002
003
004
Symbol
Parameter
Conditions
Min.
VDIFF
VP
VN
I(VP)a
Differential Supply Voltage
Pos. Supply Voltage
Neg. Supply Voltage
VP
−
VN, VDD
≤
VP
−
4 V
VN = GND, VDD
≤
VP
−
4 V
VP = 9 V, VDD = 5 V
7
7
-27
7.4
0.8
0
Typ.
Max.
36
36
0
12
1.5
10
V
V
V
mA
mA
µA
Unit
Total Device
VP Current Consumption, active NEN = lo;
NFAST = lo
NFAST = hi
VP Current Consumption, pas-
sive
NEN = open (hi), NFAST = open (hi)
005
006
I(VP)p
I(VN)a
VN Current Consumption, active NEN = lo;
NFAST = lo
NFAST = hi
VN Current Consumption, pas-
sive
Logic Supply
NEN = open (hi)
VDD = VP
−
4 V
-8.5
-1
-10
3
-5.5
-0.55
0
5.5
0
0.78
10
2.3
mA
mA
µA
V
µA
mA
007
008
009
010
I(VN)p
VDD
I(VDD)p
I(VDD)a
VDD Current Consumption, pas- NEN open (hi), NFAST open (hi)
sive
VDD Current Consumption, ac-
tive
Saturation Voltage hi
Saturation Voltage hi
V(NEN) = lo
Outputs O0, O1
101
102
Vs()hi
Vs()hi
Vs()hi = VDD
−
V(), I() = -3.2 mA
Vs()hi = VDD
−
V(), I() = -8 mA;
VDD = 3 V
VDD = 4.5 V
I() = 3.2 mA
I() = 8 mA;
VDD = 3 V
VDD = 4.5 V
VDD = 5.5 V
VDD = 3 V
VDD = 5.5 V
VDD = 3 V
1.4
0.8
10
35
35
90
50
50
250
70
70
0.1
0.25
0.2
0.12
0.35
0.3
0.2
0.5
0.4
0.25
0.7
0.6
2.4
1.7
V
V
V
V
V
V
V
V
V
V
mV
kΩ
kΩ
103
104
Vs()lo
Vs()lo
Saturation Voltage lo
Saturation Voltage lo
Logic Inputs NFAST, NEN
201 Vt()hi
Threshold Voltage hi
202
203
204
205
Vt()lo
Vhys()
Rpu()
Rpd()
Threshold Voltage lo
Input Hysteresis
Pull-Up Resistor at NFAST, NEN
referenced to VDD
Pull-Down Resistor at T0, T1, P0,
P1 referenced to GND
Input Voltage Range
Input Voltage Range
Permissible Differential Input
Voltage
Input Current at INx, IPx
Comparator Inputs INx, IPx
301
302
303
304
Vcm()fast
Vcm()
∆Vi()
I()
NFAST = lo
NFAST = hi
V(IPx)
−
V(INx)
I() = I(INx) + I(IPx);
NFAST = lo
NFAST = hi
P0 = lo (no hysteresis)
P1 = P0 = T1 = T0 = lo
P1 = lo, P0 = hi, T1 = lo, T0 = hi
P1 = lo, P0 = T1 = hi, T0 = lo
P1 = lo, P0 = hi, T1 = T0 = hi
P1 = P0 = lo, T1 = lo, T0 = hi
P1 = P0 = lo, T1 = hi, T0 = lo
0.6
6
-30
VN
−
0.1
VN
−
0.1
-VDIFF
VP
−
5
VP
−
4
VDIFF
V
V
V
50
1
0
34
66
110
200
1
10
150
4
30
µA
µA
mV
mV
mV
mV
mV
305
306
307
308
309
310
311
Vos
Vhys0
Vhys1
Vhys2
Vhys3
tHoldint0
tHoldint1
Offset VOltage
Input Hysteresis symmetrical
Input Hysteresis symmetrical
Input Hysteresis symmetrical
Input Hysteresis symmetrical
internal hold time
internal hold time
1.6
16
µs
µs
iC-HC
ULTRA FAST DUAL HV-KOMPARATOR
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Rev A1, Page 5/10
ELECTRICAL CHARACTERISTICS
Item
No.
312
313
Symbol
tHoldint2
tHold
Parameter
internal hold time
external hold time
Conditions
Min.
P1 = P0 = lo, T1 = T0 = hi
P1 = P0 = hi, T0 (T1): ext. RC network with R
referenced to VDD and C referenced to GND or
VDD
|∆Vi()| > 200 mV + Vhys in 0.5 ns, NFAST = lo;
VDD = 5 V
VDD = 3 V
NFAST = hi
tp(Ox lo
→
hi)
−
tp(Ox hi
→
lo),
symmetrical input signal;
NFAST = lo
NFAST = hi
Cl = 10 pF, Rl = 10 kΩ, VDD = 5 V,
10 %
↔
90 %
NFAST = lo, VDD = 5 V
NFAST = lo, VDD = 3 V
NFAST = hi, VDD = 3 V
P0 = P1 = hi, hold time = R * C,
Rext referenced to VDD
P0 = P1 = hi, holdtime = R * C,
Cext referenced to GND or VDD
2
0
60
0.7 *
RC
Typ.
100
RC
Max.
160
1.2 *
RC
µs
ms
Unit
Dynamic Parameters
401 tp
Propagation Delay Ix
→
Ox
9
11
20
20
20
50
ns
ns
ns
402
∆tp
Propagation Delay Difference
-25
-70
1
9
11
20
25
70
2
20
25
50
%
%
ns
ns
ns
ns
kΩ
pF
403
404
trf()
tpmin
Rise and Fall Time at O0, O1
Minimum Pulse Duration
Hold-Timer T0, T1
501
502
Rext
Cext
ext. resistor
ext. capacitor
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