QL4016-4PF84C datasheet, PDF - EEWORLD Datasheet

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QL4016-4PF84C: DescriptionField Programmable Gate Array, 320 CLBs, 61280 Gates, 320-Cell, CMOS, PQCC84, PLASTIC, LCC-84; CategoryProgrammable logic devices Programmable logic; File Size1MB，45 Pages; ManufacturerQuickLogic Corporation; Websitehttps://www.quicklogic.com

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QL4016-4PF84C Overview

Field Programmable Gate Array, 320 CLBs, 61280 Gates, 320-Cell, CMOS, PQCC84, PLASTIC, LCC-84

QL4016-4PF84C Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	QuickLogic Corporation
Parts packaging code	LCC
package instruction	QCCJ, LDCC84,1.2SQ
Contacts	84
Reach Compliance Code	compliant
JESD-30 code	S-PQCC-J84
JESD-609 code	e0
Humidity sensitivity level	3
Configurable number of logic blocks	320
Equivalent number of gates	61280
Number of entries	118
Number of logical units	320
Output times	110
Number of terminals	84
Maximum operating temperature	70 °C
Minimum operating temperature
organize	320 CLBS, 61280 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC84,1.2SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3,3.3/5 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED

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QuickRAM Family Data Sheet

• • • • • •

QuickRAM ESP Combining Performance, Density and

Embedded RAM

Device Highlights

High Performance & High Density

• Up to 90,000 usable PLD gates with up to

316 I/Os

• 300 MHz 16-bit counters, 400 MHz datapaths,

160+ MHz FIFOs

• 0.35 µm four-layer metal non-volatile CMOS

process

Up to 316 I/O Pins

• Up to 308 bi-directional input/output pins,

PCI-compliant for 5.0 V and 3.3 V buses for

-1/-2/-3/-4 speed grades

• Eight high-drive input/distributed network pins

Eight Low-Skew Distributed

Networks

• Two array clock/control networks are available to

the logic cell flip-flop; clock, set, and reset inputs

— each can be driven by an input-only pin

• Six global clock/control networks available to the

logic cell; F1, clock, set, and reset inputs and the

data input, I/O register clock, reset, and enable

inputs as well as the output enable control—each

can be driven by an input-only, I/O pin, any logic

cell output, or I/O cell feedback

High Speed Embedded SRAM

• Up to 22 dual-port RAM modules, organized in

user-configurable 1,152 bit blocks

• 5 ns access times, each port independently

accessible

• Fast and efficient for FIFO, RAM, and ROM

functions

High Performance Silicon

• Input + logic cell + output total delays under 6 ns

• Data path speeds over 400 MHz

• Counter speeds over 300 MHz

• FIFO speeds over 160+ MHz

Figure 1: QuickRAM Block Diagram

Easy to Use/Fast Development

Cycles

• 100% routable with 100% utilization and

complete pin-out stability

• Variable-grain logic cells provide high

performance and 100% utilization

• Comprehensive design tools include high quality

Verilog/VHDL synthesis

Advanced I/O Capabilities

• Interfaces with 3.3 V and 5.0 V devices

• PCI compliant with 3.3 V and 5.0 V busses for

-1/-2/-3/-4 speed grades

• Full JTAG boundary scan

• I/O cells with individually controlled registered

input path and output enables

www.quicklogic.com

•

RAM

Blocks

1,584

Hi gh Speed

Logic Cells

Interface

•

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