QL3006 pASIC 3 FPGA Data Sheet
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6,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance
and High Density
Device Highlights
High Performance and High
Density
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6,000 usable PLD gates with 82 I/Os
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300 MHz 16-bit counters,
Four Low-Skew Distributed
Networks
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Two array clock/control networks available
to the logic cell flip-flop clock, set and reset
inputs — each driven by an input-only pin
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Two global clock/control networks available
400 MHz datapaths
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0.35
µm
four-layer metal non-volatile CMOS
process for smallest die sizes
Easy-to-Use / Fast Development
Cycles
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100% routable with 100% utilization and
to the logic cell; F1, clock, set and reset
inputs and the data input, I/O register clock,
reset and enable inputs as well as the output
enable control — each driven by an input-
only or I/O pin, or any logic cell output or
I/O cell feedback
High Performance
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Input + logic cell + output total delays
complete pin-out stability
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Variable-grain logic cells provide high
under 6 ns
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Data path speeds over 400 MHz
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Counter speeds over 300 MHz
performance and 100% utilization
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Comprehensive design tools include high
quality Verilog/VHDL synthesis
Advanced I/O Capabilities
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Interfaces with 3.3 and 5.0 V devices
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PCI compliant with 3.3 and 5.0 V buses
for -1/-2/-3/-4 speed grades
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Full JTAG boundary scan
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I/O Cells with individually controlled
Registered Input Path and Output Enables
Total of 82 I/O pins
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74 bidirectional input/output pins,
PCI-compliant for 3.3 and 5.0 V buses for
-1/-2/-3/-4 speed grades
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Four high-drive input-only pins
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Four high-drive input-only/distributed
Figure 1: 160 pASIC 3 Logic Cells
network pins
© 2003 QuickLogic Corporation
www.quicklogic.com
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QL3006 pASIC 3 FPGA Data Sheet Rev C
Architecture Overview
The QL3006 is a 6,000 usable PLD gate member of the pASIC 3 family of FPGAs. pASIC 3
FPGAs are fabricated on a 0.35
µm
four-layer metal process using QuickLogic
patented
ViaLink
technology to provide a unique combination of high performance, high density, low
cost, and extreme ease-of-use.
The QL3006 contains 160 logic cells. With a maximum of 82 I/Os, the QL3006 is available in
68-pin PLCC, 84-pin PLCC, and 100-pin TQFP packages.
Software support for the complete pASIC 3 family, including the QL3006, is available through
three basic packages. The turnkey QuickWorks
package provides the most complete FPGA
software solution from design entry to logic synthesis, to place and route, to simulation. The
QuickTools
TM
for Workstations package provides a solution for designers who use Cadence
,
Exemplar
TM
, Mentor
, Synopsys
, Synplicity
, Viewlogic
TM
, Aldec
TM
, or other third-party tools
for design entry, synthesis, or simulation.
Electrical Specifications
AC Characteristics at V
CC
= 3.3 V, TA = 25°C (K = 1.00)
To calculate delays, multiply the appropriate K factor from
Table 7
by the numbers provided in
Table 1
through
Table 5.
Table 1: Logic Cells
Symbol
Parameter
1
t
PD
t
SU
t
H
t
CLK
t
CWHI
t
CWLO
t
SET
t
RESET
t
SW
t
RW
Combinatorial Delay
Setup Time
Hold Time
Clock to Q Delay
Clock High Time
Clock Low Time
Set Delay
Reset Delay
Set Width
Reset Width
b
b
Propagation Delays (ns) Fanout
a
2
1.7
1.7
0.0
1.0
1.2
1.2
1.3
1.1
1.9
1.8
3
1.9
1.7
0.0
1.2
1.2
1.2
1.5
1.3
1.9
1.8
4
2.2
1.7
0.0
1.5
1.2
1.2
1.8
1.6
1.9
1.8
8
3.2
1.7
0.0
2.5
1.2
1.2
2.8
2.6
1.9
1.8
1.4
1.7
0.0
0.7
1.2
1.2
1.0
0.8
1.9
1.8
a. Stated timing for worst case Propagation Delay over process variation at V
CC
= 3.3 V and
TA = 25
°
C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature
settings as specified in
Table 7
.
b. These limits are derived from a representative selection of the slowest paths through the pASIC
3 logic cell including typical net delays. Worst case delay values for specific paths should be
determined from timing analysis of your particular design.
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© 2003 QuickLogic Corporation
QL3006 pASIC 3 FPGA Data Sheet Rev C
Table 2: Input-Only/Clock Cells
Symbol
Parameter
1
t
IN
t
INI
t
ISU
t
IH
t
lCLK
t
lRST
t
lESU
t
lEH
High Drive Input Delay
High Drive Input, Inverting Delay
Input Register Set-Up Time
Input Register Hold Time
Input Register Clock To Q
Input Register Reset Delay
Input Register clock Enable Set-Up Time
Input Register Clock Enable Hold Time
1.5
1.6
3.1
0.0
0.7
0.6
2.3
0.0
Propagation Delays (ns) Fanout
a
2
1.6
1.7
3.1
0.0
0.8
0.7
2.3
0.0
3
1.8
1.9
3.1
0.0
1.0
0.9
2.3
0.0
4
1.9
2.0
3.1
0.0
1.1
1.0
2.3
0.0
8
2.4
2.5
3.1
0.0
1.6
1.5
2.3
0.0
12
2.9
3.0
3.1
0.0
2.1
2.0
2.3
0.0
24
4.4
4.5
3.1
0.0
3.6
3.5
2.3
0.0
a. Stated timing for worst case Propagation Delay over process variation at V
CC
= 3.3 V and
TA = 25
°
C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and
temperature settings as specified in
Table 7
.
Table 3: Clock Cells
Symbol
Parameter
Propagation Delays (ns) Loads per Half Column
a
1
t
ACK
t
GCKP
t
GCKB
Array Clock Delay
Global Clock Pin Delay
Global Clock Buffer Delay
1.2
0.7
0.8
2
1.2
0.7
0.8
3
1.3
0.7
0.9
4
1.3
0.7
0.9
8
1.5
0.7
1.1
10
1.6
0.7
1.2
11
1.7
0.7
1.3
a. The array distributed networks consist of 32 half columns and the global distributed networks
consist of 36 half columns, each driven by an independent buffer. The number of half columns
used does not affect clock buffer delay. The array clock has up to eight loads per half column. The
global clock has up to eleven loads per half column.
© 2003 QuickLogic Corporation
www.quicklogic.com
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QL3006 pASIC 3 FPGA Data Sheet Rev C
Table 4: Input-Only I/O Cells
Symbol
Parameter
Propagation Delays (ns) Fanout
a
1
t
I/O
t
ISU
t
IH
t
lOCLK
t
lORST
t
lESU
t
lEH
Input Delay (bidirectional pad)
Input Register Set-Up Time
Input Register Hold Time
Input Register Clock To Q
Input Register Reset Delay
Input Register clock Enable Set-Up Time
Input Register Clock Enable Hold Time
1.3
3.1
0.0
0.7
0.6
2.3
0.0
2
1.6
3.1
0.0
1.0
0.9
2.3
0.0
3
1.8
3.1
0.0
1.2
1.1
2.3
0.0
4
2.1
3.1
0.0
1.5
1.4
2.3
0.0
8
3.1
3.1
0.0
2.5
2.4
2.3
0.0
10
3.6
3.1
0.0
3.0
2.9
2.3
0.0
a. Stated timing for worst case Propagation Delay over process variation at V
CC
= 3.3 V and
TA = 25
°
C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature
settings as specified in
Table 7
.
Table 5: Output-Only I/O Cells
Symbol
Parameter
30
t
OUTLH
t
OUTHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Output Delay Low to High
Output Delay High to Low
Output Delay Tri-state to High
Output Delay Tri-state to Low
Output Delay High to Tri-State
Output Delay Low to Tri-State
a
Propagation Delays (ns) Output Load
Capacitance (pF)
50
2.5
2.6
1.7
2.0
-
-
75
3.1
3.2
2.2
2.6
-
-
100
3.6
3.7
2.8
3.1
-
-
150
4.7
4.8
3.9
4.2
-
-
2.1
2.2
1.2
1.6
2.0
1.2
a. The loads presented in
Figure 2
are used for t
PXZ
:
t
PHZ
1ΚΩ
5 pF
1ΚΩ
t
PLZ
5 pF
Figure 2: Loads used for t
PXZ
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© 2003 QuickLogic Corporation
QL3006 pASIC 3 FPGA Data Sheet Rev C
DC Characteristics
The DC specifications are provided in
Table 6
through
Table 8.
Table 6: Absolute Maximum Ratings
Parameter
V
CC
Voltage
V
CCIO
Voltage
Input Voltage
Latch-up Immunity
Value
-0.5 V to 4.6 V
-0.5 V to 7.0 V
-0.5 V to V
CCIO
+0.5 V
±200 mA
Parameter
DC Input Current
ESD Pad Protection
Storage Temperature
Lead Temperature
Value
±20 mA
±2000 V
-65°C to +150°C
300°C
Table 7: Operating Range
Symbol
Parameter
Military
Min
V
CC
V
CCIO
TA
TC
Supply Voltage
I/O Input Tolerance Voltage
Ambient Temperature
Case Temperature
-0 Speed Grade
-1 Speed Grade
K
Delay Factor
-2 Speed Grade
-3 Speed Grade
-4 Speed Grade
3.0
3.0
-55
-
-
0.42
0.42
Max
3.6
5.5
-
125
-
1.64
1.37
Industrial
Min
3.0
3.0
-40
-
0.43
0.43
0.43
0.43
0.43
Max
3.6
5.5
85
-
1.90
1.54
1.28
0.90
0.82
Commercial
Min
3.0
3.0
0
-
0.46
0.46
0.46
0.46
0.46
Max
3.6
5.25
70
-
1.85
1.50
1.25
0.88
0.80
V
V
°C
°C
n/a
n/a
n/a
n/a
n/a
Unit
© 2003 QuickLogic Corporation
www.quicklogic.com
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