QL8250--7PS484I datasheet, PDF

Eclipse II Family Data Sheet

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Ultra-Low Power FPGA Combining Performance, Density, and

Embedded RAM

Device Highlights

Flexible Programmable Logic

• As low as 14 µA standby current

• 0.18 µm, six layer metal CMOS process

• 1.8 V VCC, 1.8/2.5/3.3 V drive capable I/O

• Up to 4,002 dedicated flip-flops

• Up to 55.3 K embedded SRAM bits

• Up to 310 I/O

• Up to 335 user available pins

• Up to 320 K system gates

• IEEE 1149.1 boundary scan testing compliant

Advanced Clock Network

• Multiple dedicated low skew clock networks

• High drive input-only networks

• Quadrant-based segmentable clock networks

• User programmable Phase Locked Loops (PLL)

Embedded Computational Units

(ECUs)

Hardwired DSP building blocks with integrated

Multiply, Add, and Accumulate functions.

Security Features

The QuickLogic products come with secure

ViaLink® technology that protects intellectual

property from design theft and reverse engineering.

No external configuration memory needed;

instant-on at power-up.

Figure 1: Eclipse II Block Diagram

PLL

Embedded RAM Blocks

Embeded Computational Units

PLL

Embedded Dual Port SRAM

• Up to twenty-four 2,304 bit dual port high

performance SRAM blocks

• RAM/ROM/FIFO wizard for automatic

configuration

• Configurable and cascadable aspect ratio

Programmable I/O

• High performance I/O cell

• Programmable slew rate control

• Programmable I/O standards:

LVTTL, LVCMOS, LVCMOS18, PCI, GTL+,

SSTL2, and SSTL3

Independent I/O banks capable of supporting

multiple standards in one device

I/O register configurations: Input, Output,

Output Enable (OE)

PLL

Fabric

Embedded RAM Blocks

PLL

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Eclipse II Family Data Sheet Rev. R

Table 1: Eclipse II Product Family Members

QL8025

Max Gates

Logic Array

Logic Cells

Max Flip-Flops

Max I/O

RAM Modules

RAM Bits

PLLs

ECUs

VQFP

CTBGA (0.5 mm)

TQFP

Packages

TFBGA (0.8 mm)

TFBGA (0.5 mm)

PQFP

LFBGA (0.8 mm)

PBGA (1.0 mm)

47,052

16 x 8

128

532

92

4

9,216

-

100

-

144

196

-

QL8050

63,840

16 x 16

256

884

124

4

9,216

-

100

101

144

196

-

QL8150

188,946

32 x 20

640

1,709

165

16

36,864

-

144

196

208

280

-

QL8250

248,160

40 x 24

960

2,670

250

20

46,100

4

10

-

208

280

484

QL8325

320,640

48 x 32

1,536

4,002

310

24

55,300

4

12

-

208

280

484

Table 2: Max I/O per Device/Package Combination

Device

QL8025

QL8050

QL8150

QL8250

QL8325

100 VQFP

62

-

101 CTBGA

196 TFBGA 196 TFBGA

144 TQFP

208 PQFP 280 LFBGA 484 PBGA

(0.5 mm)

(0.8 mm)

(0.5 mm)

-

72

-

92

100

-

92

124

-

148

-

143

115

-

165

163

-

250

310

QuickWorks® Design Software

The QuickWorks package provides the most complete ESP and FPGA software solution from design entry to

logic synthesis, to place and route, to power calculation, and simulation. The package provides a solution for

designers who use third-party tools from Cadence, Mentor, OrCAD, Synopsys, Viewlogic, and other third-

party tools for design entry, synthesis, or simulation.

Process Data

Eclipse II is fabricated on a 0.18

μ

, six layer metal CMOS process. The core voltage is 1.8 V and the I/Os are

up to 3.3 V drive/tolerant. The Eclipse II product line is available in commercial, industrial, and military

temperature grades.

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Eclipse II Family Data Sheet Rev. R

Programmable Logic Architectural Overview

The Eclipse II logic cell structure is presented in

Figure 2.

This architectural feature addresses today's register-

intensive designs.

Table 3: Performance Standards

Function

Multiplexer

Parity Tree

Counter

Description

16:1

24

36

16 bit

32 bit

128 x 32

FIFO

Clock-to-Out

System clock

128 x 64

256 x 16

Slowest Speed Grade

2.8 ns

3.4 ns

4.6 ns

275 MHz

250 MHz

197 MHz

188 MHz

208 MHz

4 ns

200 MHz

Fastest Speed Grade

2.4 ns

2.9 ns

3.9 ns

328 MHz

300 MHz

235 MHz

266 MHz

248 MHz

3.3 ns

300 MHz

The Eclipse II logic cell structure presented in

Figure 2

is a dual register, multiplexer-based logic cell. It is

designed for wide fan-in and multiple, simultaneous output functions. Both registers share CLK, SET, and

RESET inputs. The second register has a two-to-one multiplexer controlling its input. The register can be

loaded from the NZ output or directly from a dedicated input.

NOTE:

The input PP is not an “input” in the classical sense. It is a static input to the logic cell and selects

which path (NZ or PS) is used as an input to the Q2Z register. All other inputs are dynamic and can

be connected to multiple routing channels.

The complete logic cell consists of two six-input AND gates, four two-input AND gates, seven two-to-one

multiplexers, and two D flip-flops with asynchronous SET and RESET controls. The cell has a fan-in of 30

(including register control lines), fits a wide range of functions with up to 17 simultaneous inputs, and has six

outputs (four combinatorial and two registered). The high logic capacity and fan-in of the logic cell

accommodates many user functions with a single level of logic delay while other architectures require two or

more levels of delay.

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Eclipse II Family Data Sheet Rev. R

Figure 2: Eclipse II Logic Cell

QS

A1

A2

A3

A4

A5

A6

OS

OP

B1

B2

C1

C2

MP

MS

D1

D2

E1

E2

NP

NS

F1

F2

F3

F4

F5

F6

PS

PP

QC

QR

AZ

OZ

QZ

NZ

Q2Z

FZ

RAM Modules

The Eclipse II Product Family includes up to 24 dual-port 2,304-bit RAM modules for implementing RAM,

ROM, and FIFO functions. Each module is user-configurable into two different block organizations and can be

cascaded horizontally to increase their effective width, or vertically to increase their effective depth as shown

in

Figure 4.

Figure 3: 2,304-bit RAM Module

MODE[1:0]

WA[7:0]

WD[17:0]

WE

WCLK

ASYNCRD

RA[7:0]

RD[17:0]

RE

RCLK

The number of RAM modules varies from 4 to 24 blocks for a total of 9.2 K to 55.3 K bits of RAM. Using

the two “mode” pins, designers can configure each module into 128 x 18 and 256 x 9. The blocks are also

easily cascadable to increase their effective width and/or depth (see

Figure 4

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Eclipse II Family Data Sheet Rev. R

Figure 4: Cascaded RAM Modules

WDATA

WADDR

RAM

Module

(2,304 bits)

RDATA

RADDR

WDATA

RAM

Module

(2,304 bits)

RDATA

The RAM modules are dual-port, with completely independent READ and WRITE ports and separate READ

and WRITE clocks. The READ ports support asynchronous and synchronous operation, while the WRITE

ports support synchronous operation. Each port has 18 data lines and 8 address lines, allowing word lengths

of up to 18 bits and address spaces of up to 256 words. Depending on the mode selected, however, some

higher order data or address lines may not be used.

The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read Enable (RE) acts

as a clock enable for synchronous READ operation (ASYNCRD input low), or as a flow-through enable for

asynchronous READ operation (ASYNCRD input high).

Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by

connecting corresponding address lines together and dividing the words between modules.

A similar technique can be used to create depths greater than 256 words. In this case address signals higher

than the MSB are encoded onto the write enable (WE) input for WRITE operations. The READ data outputs

are multiplexed together using encoded higher READ address bits for the multiplexer SELECT signals.

The RAM blocks can be loaded with data generated internally (typically for RAM or FIFO functions) or with

data from an external PROM (typically for ROM functions).

Embedded Computational Unit (ECU)

Traditional Programmable Logic architectures do not implement arithmetic functions efficiently or effectively—

these functions require high logic cell usage while garnering only moderate performance results.

The Eclipse II architecture allows for functionality above and beyond that achievable using programmable logic

devices. By embedding a dynamically reconfigurable computational unit, the Eclipse II device can address

various arithmetic functions efficiently. This approach offers greater performance and utilization than

traditional programmable logic implementations. The embedded block is implemented at the transistor level

as shown in

Figure 5.

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Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	QuickLogic Corporation
Parts packaging code	BGA
package instruction	BGA,
Contacts	484
Reach Compliance Code	compliant
Combined latency of CLB-Max	1.3132 ns
JESD-30 code	R-PBGA-B484
JESD-609 code	e0
length	23 mm
Humidity sensitivity level	3
Configurable number of logic blocks	960
Equivalent number of gates	248160
Number of terminals	484
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	960 CLBS, 248160 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	2.34 mm
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	23 mm

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