• Available in Pb-Free and non Pb-Free 48-ball FBGA and
a 44-lead TSOP Type II packages
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 90% when addresses are not
toggling. The device can be put into standby mode reducing
power consumption by more than 99% when deselected (CE
HIGH or both BHE and BLE are HIGH). The input/output pins
(I/O
0
through I/O
15
) are placed in a high-impedance state
when: deselected (CE HIGH), outputs are disabled (OE
HIGH), both Byte High Enable and Byte Low Enable are
disabled (BHE, BLE HIGH) or during a write operation (CE
LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
15
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
15
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes
.
Functional Description
[1]
The CY62127DV30 is a high-performance CMOS static RAM
organized as 64K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL
®
) in
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
10
ROW DECODER
64K x 16
RAM Array
2048 x 512
SENSE AMPS
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
CE
BHE
BLE
A
11
Pow -Down
er
Circuit
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
A
12
A
13
A
14
A
15
Cypress Semiconductor Corporation
Document #: 38-05229 Rev. *H
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 19, 2006
CY62127DV30
Product Portfolio
Power Dissipation
Operating, I
CC
(mA)
V
CC
Range (V)
Product
CY62127DV30L
CY62127DV30LL
CY62127DV30L
CY62127DV30LL
CY62127DV30L
CY62127DV30LL
2.2
2.2
2.2
3.0
3.0
3.0
3.6
3.6
3.6
Min.
2.2
Typ.
3.0
Max.
3.6
Speed
(ns)
45
45
55
55
70
70
f = 1 MHz
Typ
[4]
0.85
0.85
0.85
0.85
0.85
0.85
Max.
1.5
1.5
1.5
1.5
1.5
1.5
Typ.
[4]
6.5
6.5
5
5
5
5
f = f
MAX
Max.
13
13
10
10
10
10
Range
Ind’l
Ind’l
Ind’l
Auto
Ind’l
Ind’l
Ind’l
Standby I
SB2
(µA)
Typ.
[4]
1.5
1.5
1.5
1.5
1.5
1.5
1.5
Max.
5
4
5
15
4
5
4
Pin Configurations
[2, 3]
FBGA (Top View)
4
2
5
3
OE
BHE
I/O
10
I/O
11
A
0
A
3
A
5
NC
A
1
A
4
A
6
A
7
NC
A
15
A
13
A
10
A
2
CE
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
TSOP II (Forward)
Top View
1
BLE
I/O
8
I/O
9
V
SS
V
CC
6
NC
I/O
0
I/O
2
V
CC
V
SS
I/O
6
I/O
7
NC
A
B
C
D
E
F
G
H
I/O
12
DNU
A
14
A
12
A
9
I/O
14
I/O
13
I/O
15
NC
NC
A
8
A
4
A
3
A
2
A
1
A
0
CE
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
V
SS
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
15
A
14
A
13
A
12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
5
A
6
A
7
OE
BHE
BLE
I/O
15
I/O
14
I/O
13
I/O
12
V
SS
V
CC
I/O
11
I/O
10
I/O
9
I/O
8
NC
A
8
A
9
A
10
A
11
DNU
Notes:
2. NC pins are not connected to the die.
3. Pin #23 of TSOP II and E3 ball of FBGA are DNU, which have to be left floating or tied to Vss to ensure proper application. (Expansion Pins on FBGA Package:
E4 - 2M, D3 - 4M, H1 - 8M, G2 - 16M, H6 - 32M).
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25°C.
Document #: 38-05229 Rev. *H
Page 2 of 11
CY62127DV30
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Latch-up Current..................................................... > 200 mA
Operating Range
Range
Industrial
Automotive
Ambient Temperature (T
A
)
–40°C to +85°C
–40°C to +125°C
V
CC
[6]
2.2V to 3.6V
2.2V to 3.6V
DC Electrical Characteristics
(Over the Operating Range)
–45
Parameter
V
OH
V
OL
V
IH
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Test Conditions
2.2 < V
CC
< 2.7 I
OH
=
−0.1
mA
2.7 < V
CC
< 3.6 I
OH
=
−1.0
mA
2.2 < V
CC
< 2.7 I
OL
= 0.1 mA
2.7 < V
CC
< 3.6 I
OL
= 2.1 mA
2.2 < V
CC
< 2.7
2.7 < V
CC
< 3.6
V
IL
I
IX
I
OZ
Input LOW
Voltage
2.2 < V
CC
< 2.7
2.7 < V
CC
< 3.6
Ind’l
Auto
−1
+1
1.8
2.2
−0.3
−0.3
−1
2.0
2.4
0.4
0.4
V
CC
1.8
+ 0.3
V
CC
2.2
+ 0.3
0.6
0.8
+1
−0.3
−0.3
−1
−4
−1
−4
6.5
0.85
1.5
1.5
13
1.5
5
4
5
0.85
1.5
1.5
1.5
2.0
2.4
0.4
0.4
V
CC
1.8
+ 0.3
V
CC
2.2
+ 0.3
0.6
−0.3
0.8
−0.3
+1
+4
+1
+4
10
1.5
5
15
4
1.5
4
5
0.85
1.5
10
1.5
5
µA
−1
+1
−1
–55
2.0
2.4
0.4
0.4
V
CC
+ 0.3
V
CC
+ 0.3
0.6
0.8
+1
µA
µA
µA
µA
mA
V
V
V
–70
V
Min. Typ.
[4]
Max. Min. Typ.
[4]
Max. Min Typ.
[4]
Max. Unit
Input Leakage GND < V
I
< V
CC
Current
Output
Leakage
Current
GND < V
O
< V
CC
, Output Ind’l
Disabled
Auto
I
CC
V
CC
Operating f = f
MAX
= 1/t
RC
V
CC
= 3.6V,
Supply Current
I
OUT
= 0 mA,
f = 1 MHz
CMOS level
Automatic CE
Power-down
Current—
CMOS Inputs
CE > V
CC
−
0.2V,
L Ind’l
V
IN
> V
CC
−
0.2V, V
IN
Auto
< 0.2V,
f = f
MAX
(Address and LL
Data Only),
f = 0 (OE, WE, BHE
and BLE)
CE > V
CC
−
0.2V,
V
IN
> V
CC
−
0.2V or
V
IN
< 0.2V,
f = 0, V
CC
= 3.6V
L Ind’l
Auto
LL
I
SB1
I
SB2
Automatic CE
Power-down
Current—
CMOS Inputs
1.5
1.5
5
4
1.5
1.5
1.5
5
15
4
1.5
1.5
5
4
µA
Capacitance
[7]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz
V
CC
= V
CC(typ)
Max.
8
8
Unit
pF
pF
Notes:
5. V
IL(min.)
=
−2.0V
for pulse durations less than 20 ns., V
IH(max.)
= Vcc+0.75V for pulse durations less than 20 ns.
6. Full device operation requires linear ramp of V
CC
from 0V to V
CC(min)
& V
CC
must be stable at V
CC(min)
for 500
µs.
7. Tested initially and after any design or proces changes that may affect these parameters.
Document #: 38-05229 Rev. *H
Page 3 of 11
CY62127DV30
Thermal Resistance
[7]
Parameter
θ
JA
θ
JC
Description
Thermal Resistance (Junction to Ambient)
Thermal Resistance (Junction to Case)
Test Conditions
Still Air, soldered on a 3 x 4.5 inch,
two-layer printed circuit board
FBGA
55
12
TSOP II
76
11
Unit
°C/W
°C/W
AC Test Loads and Waveforms
[8]
R1
V
CC
OUTPUT
50 pF
INCLUDING
JIG AND
SCOPE
R2
V
CC
10%
GND
Rise Time = 1 V/ns
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT
R
TH
OUTPUT
V
2.5V (2.2V - 2.7V)
16600
15400
8000
1.20
3.0V (2.7V - 3.6V)
1103
1554
645
1.75
Unit
Ω
Ω
Ω
V
Parameters
R1
R2
R
TH
V
TH
Data Retention Characteristics
Parameter
V
DR
I
CCDR
Description
V
CC
for Data Retention
Data Retention Current
V
CC
=1.5V, CE > V
CC
−
0.2V,
V
IN
> V
CC
−
0.2V or V
IN
< 0.2V
L
L
LL
t
CDR[7]
t
R[9]
Chip Deselect to Data
Retention Time
Operation Recovery Time
Ind’l
Auto
Ind’l
0
200
Conditions
Min.
1.5
4
10
3
ns
µs
Typ
.[4]
Max.
Unit
V
µA
Data Retention Waveform
[10]
DATA RETENTION
MODE
DATA RETENTION
MODE
V
DR
> 1.5V
V
DR
> 1.5V
V
CC
V
CC
CE or
CE or
BHE. BLE
BHE. BLE
V
V
CC(min.)
CC(min.)
V
V CC(min.)
CC(min.)
t
CDR
t
CDR
t
t
R
R
Notes:
8. Test condition for the 45-ns part is a load capacitance of 30 pF.
9. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 200
µs.
10. BHE
.
BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the Chip Enable signals or by disabling both.
Document #: 38-05229 Rev. *H
Page 4 of 11
CY62127DV30
Switching Characteristics
(Over the Operating Range)
[11]
CY62127DV30-45
[8]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE[13]
t
HZBE
Write Cycle
[15]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BLE/BHE LOW to Write End
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z
[12,14]
WE HIGH to Low Z
[12]
10
45
40
40
0
0
35
40
25
0
15
10
55
40
40
0
0
40
40
25
0
20
5
70
60
60
0
0
50
60
30
0
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[12]
OE HIGH to High Z
[12,14]
CE LOW to Low Z
[12]
CE HIGH to High Z
[12,14]
CE LOW to Power-up
CE HIGH to Power-down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z
[12]
BLE/BHE HIGH to High-Z
[12,14]
5
15
0
45
45
5
20
10
20
0
55
55
5
25
5
15
10
20
0
70
70
10
45
25
5
20
10
25
45
45
10
55
25
5
25
55
55
10
70
35
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
CY62127DV30-55
Min.
Max.
CY62127DV30-70
Min.
Max.
Unit
Notes:
11. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of V
CC(typ.)
/2, input pulse levels of 0 to V
CC(typ.)
, and output loading of the
specified I
OL
.
12. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any
given device.
13. If both byte enables are toggled together, this value is 10 ns.
14. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high-impedance state.
15. The internal Write time of the memory is defined by the overlap of WE, CE = V
IL
, BHE and/or BLE = V
IL
. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
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