DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD6345
8 BIT SERIAL IN/PARALLEL OUT DRIVER
The
µ
PD6345 is a monolithic Bi-CMOS integrated Circuit designed to drive LED, Solenoid and Relay.
This device consists of an 8-bit shift register, latch and buffer with high voltage N-P-N Transistors (Open Collector).
Data is serially loaded into shift register on the positive-going transition of the clock. Parallel data is transferred to
the output buffers through the 8-bit latch while the latch enable input is high and latched when the latch enable is low.
When the output enable input is low, all outputs are off (High Impedance).
FEATURES
• High Speed Serially-shifted Data Input.
• Latches on all driver Outputs.
• 40 V Output Voltage Rating.
• 60 mA Output Sink Current.
• Built in power supply voltage detection circuit.
• Capable of connection to cascade additional device.
• Wide Operating Temperature Range: –40 to +85
°C
• Bi-CMOS STRUCTURE
ORDERING INFORMATION
Part Number
Package
16 Pin Plastic DIP (300 mil)
16 Pin Plastic SOP (300 mil)
µ
PD6345C
µ
PD6345GS
Document No. IC-2166A (2nd edition)
(O.D. No. IC-5437A)
Date Published March 1997 P
Printed in Japan
©
1995
1988
µ
PD6345
PIN CONFIGURATION (Top View)
V
SS
EN
LAT
SO
O
8
O
7
O
6
O
5
1
2
3
4
5
6
7
8
16 V
DD
15 RES
14 SCK
13 SIN
12 O
1
11 O
2
10 O
3
9
O
4
PIN IDENTIFICATION
Pin No.
1
2
Symbol
GND
EN
Pin name
Ground
Output Enable
Input/Output
—
Input
Function
Connection to Ground (GND) of system.
When this pin is low or open, all outputs are OFF, and data is output
during high.
When this pin is low or open, data is latched and data is through to
output during high.
4
SO
Serial data Output
Output
Serial data is output on positive-going transition of the clock.
In case of connection to cascade additional device (
µ
PD6345), this
pin will be connected to SIN terminal of additional device.
High Voltage and Current Driver Outputs.
Data is loaded to shift register on positive-going transition.
Data of SIN is loaded to shift register on positive-going transition of
SCK. Also, serial data is output from SO on positive-going transition
of SCK.
15
RES
Reset
Input
When this pin is low or open, data of shift register is all cleared, and
this device operate normally during high.
16
V
DD
Power Supply
—
Normally supply 5 V.
3
LAT
Latch Enable
Input
5 to 12
13
14
O
8
to O
1
SIN
SCK
Driver Output
Serial data Input
Clock
Output
Input
Input
2
µ
PD6345
BLOCK DIAGRAM
O
1
O
2
O
3
O
4
O
5
O
6
O
7
O
8
EN
100 kΩ
P
1
P
2
P
3
P
4
P
5
P
6
P
7
P
8
LAT
100 kΩ
SIN
100 kΩ
RES
SCK
100 kΩ
S
1
S
2
S
3
S
4
S
5
S
6
S
7
S
8
SO
100 kΩ
P
1
to P
8
; Latch Circuits
S
1
to S
8
; 8-bit Shift register
TRUTH TABLE
OUT
O
1
H
H
H
L
High Impedance
O
n
O
n – 1
S
7
SCK = CLOCK
EN = Output Enable
RES= Reset
LAT= Latch Enable
SIN = Serial data Input
OUT = Driver Output
SO = Serial data Output
* = H or L
H = High level
L = Low level
SCK
EN
RES
LAT
SIN
SO
*1
Note
H
H
H
L
*2
H
L
O
n – 1
S
7
H
H
*
NO CHANGE
NO CHANGE
S
7
L
H
*
*
High Impedance High Impedance
S
7
*
*
*
*
NO CHANGE
NO CHANGE
S
8
*
*
L
H
*
High Impedance High Impedance
L
*
H
L
*
NO CHANGE
NO CHANGE
L
*1) Seventh data S
7
of shift register is loaded to eighth data S
8
on positive-going transition of clock, and is output
to Serial data Output pin.
*2) Shift register operates normally.
3
µ
PD6345
TIMING CHART
RES
SCK
SIN
EN
LAT
O
1
O
8
SO
4
µ
PD6345
ABSOLUTE MAXIMUM RATINGS (T
a
= 25
°
C
±
2
°
C)
Supply Voltage
Input Voltage
Input Current
Logic Output Voltage
Driver Output Voltage
Driver Output Current
Logic Output Current
Power Dissipation
Operating Temperature
Storage Temperature
V
DD
V
IN
V
IN
V
SO1
V
OUT2
I
OUT
I
SO
P
D
T
opt
T
stg
–0.3 to 7.0
–0.3 to V
DD
+ 0.3
±10
–0.3 to V
DD
+ 0.3
–0.3 to 40
100
+10
–5
850 (DIP), 800 (SOP)
–40 to + 85
–55 to +150
V
V
mA
V
V
mA
mA
mW
°C
°C
RECOMMENDED OPERATING CONDITIONS
ITEM
Operating Temperature
Supply Voltage
Input Voltage
High Level Input Voltage
Low Level Input Voltage
Clock Frequency
Driver Output Voltage
SYMBOL
T
opt
V
DD
V
IN
V
IH
V
IL
f
SCK
V
OUT
0
MIN.
–40
4.0
0
0.7 V
DD
0
5.0
TYP.
MAX.
+85
6.0
V
DD
V
DD
0.2 V
DD
8
38
UNIT
°C
V
V
V
V
MHz
V
5
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