Crystal or Differential-to-Differential
Clock Fanout Buffer
8T39S08A
Datasheet
General Description
The 8T39S08A is a high-performance clock fanout buffer. The input
clock can be selected from two differential inputs or one crystal input.
The internal oscillator circuit is automatically disabled if the crystal
input is not selected. The crystal pin can be driven by a single-ended
clock. The selected signal is distributed to eight differential outputs
which can be configured as LVPECL, LVDS and HCSL outputs. In
addition, an LVCMOS output is provided. All outputs can be disabled
into a high-impedance state. The device is designed for a signal
fanout of high-frequency, low phase-noise clock and data signal. The
outputs are at a defined level when inputs are open or tied to ground.
It is designed to operate from a 3.3V or 2.5V core power supply, and
either a 3.3V or 2.5V output operating supply.
Features
•
•
•
•
•
Two differential reference clock input pairs
Differential input pairs can accept the following input levels:
LVPECL, LVDS, HCSL, HSTL and Single-ended
Crystal Oscillator Interface
Crystal input frequency range: 10MHz to 40MHz
Maximum Output Frequency
LVPECL - 2GHz
LVDS
- 2GHz
HCSL
- 250MHz
LVCMOS - 250MHz
Two banks, each has four differential output pairs that can be
configured as LVPECL or LVDS or HCSL
One single-ended reference output with synchronous enable to
avoid clock glitch
Output skew: 80ps (maximum)
(Bank A and Bank B at the same output level)
Part-to-part skew: 200ps (typical)
Additive RMS phase jitter@ 156.25MHz, (12kHz - 20MHz):
34.7fs (typical), 3.3V/ 3.3V
Supply voltage modes:
V
DD
/V
DDO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
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©2016 Integrated Device Technology, Inc.
1
May 19, 2016
8T39S08A Datasheet
Block Diagram
PullDown
PullDown
PullDown
PullDown
Pin Assignment
V
DDOB
nQB1
V
DDOB
nQB0
nQB2
nQB3
QB0
QB1
QB2
QB3
30 29 28 27 26 25 24 23 22 21
GND
SMODEB1
nCLK1
CLK1
V
DD
REFOUT
V
DDOREF
OE_SE
SMODEA1
GND
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND
SMODEB0
REF_SEL1
nCLK0
CLK0
REF_SEL0
XTAL_OUT
XTAL_IN
V
DD
SMODEA0
8T39S08A
V
DDOA
V
DDOA
QA0
nQA0
QA1
nQA1
QA2
nQA2
QA3
40-pin, 6mm x 6mm VFQFN
©2016 Integrated Device Technology, Inc.
nQA3
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May 19, 2016
8T39S08A Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Name
QA0
nQA0
V
DDOA
QA1
nQA1
V
DDOA
QA2
nQA2
QA3
nQA3
SMODEA0
V
DD
XTAL_IN
XTAL_OUT
REF_SEL0
CLK0
nCLK0
REF_SEL1
SMODEB0
GND
nQB3
QB3
nQB2
QB2
V
DDOB
nQB1
QB1
V
DDOB
nQB0
QB0
GND
SMODEB1
nCLK1
Output
Output
Power
Output
Output
Power
Output
Output
Output
Output
Input
Power
Input
Output
Input
Input
Input
Input
Input
Power
Output
Output
Output
Output
Power
Output
Output
Power
Output
Output
Power
Input
Input
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown
Pulldown
Type
Description
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Output supply pin for Bank QA outputs.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Output supply pin for Bank QA outputs.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Output driver select for Bank A outputs. See
Table 3F
for function.
LVCMOS/LVTTL interface levels.
Power supply pin.
Crystal oscillator interface.
Crystal oscillator interface.
Input clock selection. LVCMOS/LVTTL interface levels.
See
Table 3A
for function.
Non-inverting differential clock. Internally biased to 0.33V
DD.
Inverting differential clock. Internally biased to 0.4V
DD.
Input clock selection. LVCMOS/LVTTL interface levels.
See
Table 3A
for function.
Output driver select for Bank B outputs. See
Table 3G
for function.
LVCMOS/LVTTL interface levels.
Power supply ground.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Output supply pin for Bank QB outputs.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Output supply pin for Bank QB outputs.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Power supply ground.
Output driver select for Bank B outputs. See
Table 3G
for function.
LVCMOS/LVTTL interface levels.
Inverting differential clock. Internally biased to 0.4V
DD.
©2016 Integrated Device Technology, Inc.
3
May 19, 2016
8T39S08A Datasheet
Number
34
35
36
37
38
39
40
0
Name
CLK1
V
DD
REFOUT
V
DDOREF
OE_SE
SMODEA1
GND
ePAD
Input
Power
Output
Power
Input
Input
Power
Power
Type
Pullup/
Pulldown
Description
Non-inverting differential clock. Internally biased to 0.33V
DD.
Power supply pin.
Single-ended reference clock output. LVCMOS/LVTTL interface levels.
Output supply pin for REFOUT output.
Pulldown
Pulldown
Output enable. LVCMOS/LVTTL interface levels. See
Table 3B.
Output driver select for Bank A outputs. See
Table 3F
for function.
LVCMOS/LVTTL interface levels.
Power supply ground.
Connect ePAD to ground to ensure proper heat dissipation.
NOTE:
Pulldown
and
Pullup
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input
Capacitance
OE_SE,
SMODEx[1:0],
REF_SEL[1:0]
Test Conditions
Minimum
Typical
2
50
100
75
V
DDOREF
= 3.465V
V
DDOREF
= 2.625V
V
DDOREF
= 3.3V
V
DDOREF
= 2.5V
5.3
6.3
52
63
Maximum
Units
pF
k
k
k
pF
pF
Input Pulldown Resistor
Input Pullup
Resistor
Power
Dissipation
Capacitance
Output
Impedance
CLK0, CLK1
nCLK0, nCLK1
REFOUT
REFOUT
REFOUT
REFOUT
C
PD
R
OUT
©2016 Integrated Device Technology, Inc.
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May 19, 2016
8T39S08A Datasheet
Function Tables
Table 3A. REF_SELx Function Table
Control Input
REF_SEL[1:0]
00 (default)
01
10
11
CLK0, nCLK0
CLK1, nCLK1
XTAL
XTAL
Selected Input Reference Clock
Table 3B. OE_SE Function Table
1
OE_SE
0 (default)
1
REFOUT
High-Impedance
Enabled
NOTE: 1. Synchronous output enable to avoid clock glitch.
Table 3C. Input/Output Operation Table, OE_SE
Input Status
OE_SE
0 (default)
1
REF_SEL [1:0]
Don’t care
10 or 11
CLKx and nCLKx
Don’t Care
Don’t Care
CLK0 and nCLK0 are both open circuit
1
00 (default)
CLK0 and nCLK0 are tied to ground
CLK0 is high, nCLK0 is low
CLK0 is low, nCLK0 is high
CLK1 and nCLK1 are both open circuit
1
01
CLK1 and nCLK1 are tied to ground
CLK1 is high, nCLK1 is low
CLK1 is low, nCLK1 is high
Output State
REFOUT
High Impedance
Fanout crystal oscillator
Logic Low
Logic Low
Logic High
Logic Low
Logic Low
Logic Low
Logic High
Logic Low
©2016 Integrated Device Technology, Inc.
5
May 19, 2016
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