ADVANCE
8, 16 MEG x 72
REGISTERED SDRAM DIMMs
SYNCHRONOUS
DRAM MODULE
FEATURES
• JEDEC-standard 168-pin, dual in-line memory
module (DIMM)
• PC133- and PC100-compliant
• Registered inputs with one-clock delay
• Phase-lock loop (PLL) clock driver to reduce
loading
• Utilizes 133 MHz and 125 MHz SDRAM compo-
nents
• ECC-optimized pinout
• 64MB (8 Meg x 72) and 128MB (16 Meg x 72)
• Single +3.3V ±0.3V power supply
• Fully synchronous; all signals registered on
positive edge of PLL clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal SDRAM banks for hiding row access/
precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Serial Presence-Detect (SPD)
MT9LSDT872, MT9LSDT1672
For the latest data sheet revisions, please refer to the Micron
Web site:
www.micron.com/mti/msp/html/datasheet.html
PIN ASSIGNMENT (FRONT VIEW)
168-PIN DIMM
OPTIONS
• Package
168-pin DIMM (gold)
• Frequency/CAS Latency*
133 MHz/CL = 2
(7.5ns, 133 MHz SDRAMs)
133 MHz/CL = 3
(7.5ns, 133 MHz SDRAMs)
100 MHz/CL = 2
(8ns, 125 MHz SDRAM)
MARKING
G
-13E
-133
-10E
*Device latency only; extra clock cycle required due to input register.
KEY SDRAM COMPONENT
TIMING PARAMETERS
MODULE
MARKING
-13E
-133
-10E
SPEED
GRADE
-7E
-75
-8E
CAS
LATENCY
2
3
2
ACCESS
TIME
5.4ns
5.4ns
6ns
SETUP
TIME
1.5ns
1.5ns
2ns
HOLD
TIME
0.8ns
0.8ns
1ns
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
SYMBOL
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
DD
DQ14
DQ15
CB0
CB1
V
SS
NC
NC
V
DD
WE#
DQMB0
DQMB1
S0#
DNU
V
SS
A0
A2
A4
A6
A8
A10
BA1
V
DD
V
DD
CK0
PIN SYMBOL
43
V
SS
44
DNU
45
S2#
46
DQMB2
47
DQMB3
48
DNU
49
V
DD
50
NC
51
NC
52
CB2
53
CB3
54
V
SS
55
DQ16
56
DQ17
57
DQ18
58
DQ19
59
V
DD
60
DQ20
61
NC
62
NC
63 RFU (CKE1)
64
V
SS
65
DQ21
66
DQ22
67
DQ23
68
V
SS
69
DQ24
70
DQ25
71
DQ26
72
DQ27
73
V
DD
74
DQ28
75
DQ29
76
DQ30
77
DQ31
78
V
SS
79
CK2
80
NC
81
WP
82
SDA
83
SCL
84
V
DD
PIN
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
SYMBOL
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
DD
DQ46
DQ47
CB4
CB5
V
SS
NC
NC
V
DD
CAS#
DQMB4
DQMB5
RFU (S1#)
RAS#
V
SS
A1
A3
A5
A7
A9
BA0
A11
V
DD
CK1
RFU (A12)
PIN
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
SYMBOL
V
SS
CKE0
RFU (S3#)
DQMB6
DQMB7
RFU (A13)
V
DD
NC
NC
CB6
CB7
V
SS
DQ48
DQ49
DQ50
DQ51
V
DD
DQ52
NC
NC
REGE
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
CK3
NC
SA0
SA1
SA2
V
DD
NOTE:
Symbols in parentheses are not used on these modules but may be used
for other modules in this product family. They are for reference only.
8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs
ZM28_3.p65 – Rev. 4/00
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
ADVANCE
8, 16 MEG x 72
REGISTERED SDRAM DIMMs
PART NUMBERS
PART NUMBER
MT9LSDT872G-13E__
MT9LSDT872G-133__
MT9LSDT872G-10E__
MT9LSDT1672G-13E__
MT9LSDT1672G-133__
MT9LSDT1672G-10E__
CONFIGURATION
8 Meg x 72
8 Meg x 72
8 Meg x 72
16 Meg x 72
16 Meg x 72
16 Meg x 72
SYSTEM BUS SPEED
133 MHz
133 MHz
100 MHz
133 MHz
133 MHz
100 MHz
NOTE:
All part numbers end with a two-place code (not
shown), designating component and PCB revisions.
Consult factory for current revision codes. Example:
MT9LSDT1672G-133B1
GENERAL DESCRIPTION
The MT9LSDT872 and MT9LSDT1672 are high-speed
CMOS, dynamic random-access, 64MB and 128MB
memories organized in a x72 configuration. These mod-
ules use internally configured quad-bank SDRAMs with
a synchronous interface (all signals are registered on the
positive edge of clock signals CK0).
Read and write accesses to the SDRAM modules are
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the registra-
tion of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used to
select the bank and row to be accessed (BA0, BA1 select
the bank, A0-A11 select the row). The address bits
registered coincident with the READ or WRITE com-
mand are used to select the starting column location for
the burst access.
These modules provide for programmable READ or
WRITE burst lengths of 1, 2, 4, or 8 locations, or full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst se-
quence.
These modules use an internal pipelined architecture
to achieve high-speed operation. This architecture is
compatible with the 2n rule of prefetch architectures, but
it also allows the column address to be changed on every
clock cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing one of the other
three banks will hide the PRECHARGE cycles and pro-
vide seamless, high-speed, random-access operation.
These modules are designed to operate in 3.3V, low-
power memory systems. An auto refresh mode is pro-
vided, along with a power-saving, power-down mode.
All inputs and outputs are LVTTL-compatible.
SDRAM modules offer substantial advances in DRAM
operating performance, including the ability to
synchronously burst data at a high data rate with
automatic column-address generation, the ability to
interleave between internal banks in order to hide
precharge time, and the capability to randomly change
column addresses on each clock cycle during a burst
access. For more information regarding SDRAM opera-
tion, refer to the 64Mb, 128Mb x4, x8, x16 SDRAM data
sheets.
PLL AND REGISTER OPERATION
These modules can be operated in either registered
mode (REGE pin HIGH), where the control/address
input signals are latched in the register on one rising
clock edge and sent to the SDRAM devices on the
following rising clock edge (data access is delayed by one
clock), or in buffered mode (REGE pin LOW) where the
input signals pass through the register/buffer to the
SDRAM devices on the same clock. A phase-lock loop
(PLL) on the modules is used to redrive the clock signals
to the SDRAM devices to minimize system clock loading
(CK0 is connected to the PLL, and CK1, CK2 and CK3 are
terminated).
SERIAL PRESENCE-DETECT OPERATION
These modules incorporate serial presence-detect
(SPD). The SPD function is implemented using a 2,048-
bit EEPROM. This nonvolatile storage device contains
256 bytes. The first 128 bytes can be programmed by
Micron to identify the module type and various SDRAM
organizations and timing parameters. The remaining
128 bytes of storage are available for use by the customer.
System READ/WRITE operations between the master
(system logic) and the slave EEPROM device (DIMM)
occur via a standard IIC bus using the DIMM’s SCL
(clock) and SDA (data) signals, together with SA(2:0),
which provide eight unique DIMM/EEPROM addresses.
8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs
ZM28_3.p65 – Rev. 4/00
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
ADVANCE
8, 16 MEG x 72
REGISTERED SDRAM DIMMs
SPD CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (Fig-
ures 1 and 2).
SPD ACKNOWLEDGE
Acknowledge is a software convention used to
indicate successful data transfers. The transmitting
device, either master or slave, will release the bus after
transmitting eight bits. During the ninth clock cycle,
the receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (Figure 3).
The SPD device will always respond with an ac-
knowledge after recognition of a start condition and
its slave address. If both the device and a WRITE
operation have been selected, the SPD device will re-
spond with an acknowledge after the receipt of each
subsequent eight-bit word. In the read mode the SPD
device will transmit eight bits of data, release the SDA
line and monitor the line for an acknowledge. If an
acknowledge is detected and no stop condition is
generated by the master, the slave will continue to
transmit data. If an acknowledge is not detected, the
slave will terminate further data transmissions and
await the stop condition to return to standby power
mode.
SPD START CONDITION
All commands are preceded by the start condition,
which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has
been met.
SPD STOP CONDITION
All communications are terminated by a stop con-
dition, which is a LOW-to-HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the SPD device into standby power mode.
SCL
SCL
SDA
DATA STABLE
DATA
CHANGE
DATA STABLE
SDA
START
BIT
STOP
BIT
Figure 1
Data Validity
Figure 2
Definition of Start and Stop
SCL from Master
8
9
Data Output
from Transmitter
Data Output
from Receiver
Acknowledge
Figure 3
Acknowledge Response from Receiver
8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs
ZM28_3.p65 – Rev. 4/00
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
ADVANCE
8, 16 MEG x 72
REGISTERED SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
MT9LSDT872 (64MB) AND MT9LSDT1672 (128MB)
RS0#
RDQMB0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
RDQMB1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM CS#
DQ0
DQ1 U2
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS#
DQ0
DQ1 U12
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
RDQMB6
DQM CS#
DQ0
DQ1 U3
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS#
DQ0
DQ1 U4
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
RDQMB7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQM CS#
DQ0
DQ1 U10
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS#
DQ0
DQ1 U11
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS#
DQ0
DQ1 U1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
RDQMB4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
RDQMB5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQM CS#
DQ0
DQ1 U13
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS#
DQ0
DQ1 U14
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
RS2#
RDQMB2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
RDQMB3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
U5, U7
RAS#
CAS#
CKE0
WE#
A0-A11
BA0
BA1
S0#, S2#
DQMB0-DQMB7
PLL CLK
10K
V
DD
REGE
U8
R
E
G
I
S
T
E
R
RRAS#: SDRAMs U0-U8
RCAS#: SDRAMs U0-U8
RCKE0: SDRAMs U0-U8
RWE#: SDRAMs U0-U8
RA0-RA11: SDRAMs U0-U8
RBA0: SDRAMs U0-U8
RBA1: SDRAMs U0-U8
RS0#, RS2#
RDQMB0-RDQMB7
V
DD
SCL
WP
47K
SPD
U9
A0 A1 A2
SA0 SA1 SA2
V
SS
SDA
CK1-CK3
CK0
U6
PLL
12pF
SDRAM x 3
SDRAM x 3
SDRAM x 3
REGISTER x 2
12pF
SDRAMs U0-U8
SDRAMs U0-U8
U0-U8 = MT48LC8M8A2TG SDRAMs for 64MB
U0-U8 = MT48LC16M8A2TG SDRAMs for 128MB
NOTE:
1. All resistor values are 10 ohms unless otherwise specified.
8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs
ZM28_3.p65 – Rev. 4/00
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
ADVANCE
8, 16 MEG x 72
REGISTERED SDRAM DIMMs
PIN DESCRIPTIONS
PIN NUMBERS
27, 111, 115
42, 79, 125, 163
128
SYMBOL
WE#, CAS#,
RAS#
CK0-CK3
CKE0
TYPE
Input
Input
Input
DESCRIPTION
Command Inputs: WE#, RAS#, and CAS# (along with S0#, S2#)
define the command being entered.
Clock: CK0 is distributed through an on-board PLL to all devices.
CK1-CK3 are terminated.
Clock Enable: CKE0 activates (HIGH) and deactivates (LOW) the
CK0 signal. Deactivating the clock provides POWER-DOWN and
SELF REFRESH operation (all banks idle) or CLOCK SUSPEND
operation (burst access in progress). CKE0 is synchronous except
after the device enters power-down and self refresh modes,
where CKE0 becomes asynchronous until after exiting the same
mode. The input buffers, including CK0, are disabled during
power-down and self refresh modes, providing low standby
power.
Chip Select: S0#, S2# enable (registered LOW) and disable
(registered HIGH) the command decoder. All commands are
masked when S0#, S2# are registered HIGH. S0#, S2# are
considered part of the command code.
Input/Output Mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (two-clock
latency) when DQMB is sampled HIGH during a READ cycle.
Bank Address: BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE or PRECHARGE command is being applied.
Address Inputs: A0-A11 are sampled during the ACTIVE command
(row-address A0-A11) and READ/WRITE command (column-address
A0-A8/A9, with A10 defining auto precharge) to select one
location out of the memory array in the respective bank. A10 is
sampled during a PRECHARGE command to determine if both
banks are to be precharged (A10 HIGH). The address inputs also
provide the op-code during a LOAD MODE REGISTER command.
Write Protect: Serial presence-detect hardware write protect.
Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Presence-Detect Address Inputs: These pins are used to configure
the presence-detect device.
Register Enable.
Data I/Os: Data bus.
30, 45
S0#, S2#
Input
28-29, 46-47,
112-113, 130-131
DQMB0-
DQMB7
Input
122, 39
33, 117, 34, 118, 35, 119,
36, 120, 37, 121, 38, 123
BA0, BA1
A0-A11
Input
Input
81
83
165-167
147
2-5, 7-11, 13-17, 19-20,
55-58, 60, 65-67, 69-72,
74-77, 86-89, 91-95,
97-101, 103-104,
139-142, 144, 149-151,
153-156, 158-161
21-22,0 52-53, 105-106,
136-137
WP
SCL
SA0-SA2
REGE
DQ0-DQ63
Input
Input
Input
Input
Input/
Output
CB0-CB7
Input/
Output
Check Bits.
8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs
ZM28_3.p65 – Rev. 4/00
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
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