L7C197
DEVICES INCORPORATED
256K x 1 Static RAM
L7C197
DEVICES INCORPORATED
256K x 1 Static RAM
DESCRIPTION
The
L7C197
is a high-performance,
low-power CMOS static RAM. The
storage circuitry is organized as
262,144 words by 1 bit per word. This
device is available in four speeds with
maximum access times from 15 ns
to 35 ns.
Operation is from a single +5 V power
supply and all interface signals are
TTL compatible. Power consumption
is 165 mW (typical) at 35 ns. Dissipa-
tion drops to 50 mW (typical) when
the memory is deselected.
Two standby modes are available.
Proprietary Auto-Powerdown™
circuitry reduces power consumption
automatically during read or write
accesses which are longer than the
minimum access time, or when the
memory is deselected. In addition,
data may be retained in inactive
storage with a supply voltage as low
as 2 V. The L7C197 consumes only
150 µW (typical) at 3 V, allowing
effective battery backup operation.
The L7C197 provides asynchronous
(unclocked) operation with matching
access and cycle times. An active-low
Chip Enable and a three-state output
simplify the connection of several
chips for increased capacity.
Memory locations are specified on ad-
dress pins A
0
through A
17
. Reading
from a designated location is accom-
plished by presenting an address and
driving CE LOW while WE remains
HIGH. The data in the addressed
memory location will then appear on
the Data Out pin within one access
time. The output pin stays in a high-
impedance state when CE is HIGH or
WE is LOW.
Writing to an addressed location is
accomplished when the active-low CE
and WE inputs are both LOW. Either
signal may be used to terminate the
write operation. Data In and Data Out
signals have the same polarity.
Latchup and static discharge pro-
tection are provided on-chip. The
L7C197 can withstand an injection
current of up to 200 mA on any pin
without damage.
FEATURES
q
256K x 1 Static RAM with Separate
I/O, Chip Select Powerdown
q
Auto-Powerdown™ Design
q
Advanced CMOS Technology
q
High Speed — to 15 ns maximum
q
Low Power Operation
Active: 165 mW typical at 35 ns
Standby: 5 mW typical
q
Data Retention at 2 V for Battery
Backup Operation
q
Available 100% Screened to
MIL-STD-883, Class B
q
Plug Compatible with IDT71257,
Cypress CY7C197
q
Package Styles Available:
• 24-pin Plastic DIP
• 24-pin Ceramic DIP
• 24-pin Plastic SOJ
• 28-pin Ceramic LCC
1
2
3
4
5
6
7
8
9
10
11
L7C197 B
LOCK
D
IAGRAM
D
IN
ROW SELECT
ROW
ADDRESS
10
1024 x 256
MEMORY
ARRAY
CE
WE
COLUMN SELECT
& COLUMN SENSE
8
COLUMN ADDRESS
D
OUT
256K Static RAMs
4-3
03/05/95–LDS.197-F
L7C197
DEVICES INCORPORATED
256K x 1 Static RAM
NOTES
1. Maximum Ratings indicate stress specifi-
cations only. Functional operation of these
products at values beyond those indicated
in the Operating Conditions table is not
implied. Exposure to maximum rating con-
ditions for extended periods may affect re-
liability of the tested device.
2. The products described by this specifica-
tion include internal circuitry designed to
protect the chip from damaging substrate
injection currents and accumulations of
static charge. Nevertheless, conventional
precautions should be observed during
storage, handling, and use of these circuits
in order to avoid exposure to excessive elec-
trical stress values.
3. This product provides hard clamping of
transient undershoot. Input levels below
ground will be clamped beginning at –0.6 V.
A current in excess of 100 mA is required to
reach –2.0 V. The device can withstand in-
definite operation with inputs as low as –3 V
subject only to power dissipation and bond
wire fusing constraints.
4. Tested with GND
≤
V
OUT
≤
V
CC
. The
device is disabled, i.e., CE =
V
CC
.
5. A series of normalized curves is available
to supply the designer with typical DC and
AC parametric information for Logic Devices
Static RAMs. These curves may be used to
determine device characteristics at various
temperatures and voltage levels.
6. Tested with all address and data inputs
changing at the maximum cycle rate. The
device is continuously enabled for writing,
i.e., CE
≤
V
IL
, WE
≤
V
IL
. Input pulse levels
are 0 to 3.0 V.
7. Tested with outputs open and all address
and data inputs changing at the maximum
read cycle rate. The device is continuously
disabled, i.e., CE
≥
V
IH
.
8. Tested with outputs open and all address
and data inputs stable. The device is con-
tinuously disabled, i.e., CE =
V
CC
. Input
levels are within 0.2 V of
V
CC
or GND.
9. Data retention operation requires that
V
CC
never drop below 2.0 V. CE must be
≥
V
CC
– 0.2 V. All other inputs must meet
V
IN
≥
V
CC
– 0.2 V or
V
IN
≤
0.2 V to ensure
full powerdown. For low power version (if
applicable), this requirement applies only to
CE and WE; there are no restrictions on data
and address.
10. These parameters are guaranteed but
not 100% tested.
11. Test conditions assume input transition
times of less than 3 ns, reference levels of
1.5 V, output loading for specified
I
OL
and
I
OH
plus 30 pF (Fig. 1a), and input pulse
levels of 0 to 3.0 V (Fig. 2).
12. Each parameter is shown as a minimum
or maximum value. Input requirements are
specified from the point of view of the exter-
nal system driving the chip. For example,
t
AVEW
is specified as a minimum since the
external system must supply at least that
much time to meet the worst-case require-
ments of all parts. Responses from the inter-
nal circuitry are specified from the point of
view of the device. Access time, for ex-
ample, is specified as a maximum since
worst-case operation of any device always
provides data within that time.
13. WE is high for the read cycle.
14. The chip is continuously selected (CE
low).
15. All address lines are valid prior-to or
coincident-with the CE transition to active.
16. The internal write cycle of the memory
is defined by the overlap of CE active and
WE low. All three signals must be active to
initiate a write. Any signal can terminate a
write by going inactive. The address, data,
and control input setup and hold times
should be referenced to the signal that be-
comes active last or becomes inactive first.
17. If WE goes low before or concurrent
with the latter of CE going active, the output
remains in a high impedance state.
18. If CE goes inactive before or concurrent
with WE going high, the output remains in
a high impedance state.
19. Powerup from
I
CC2
to
I
CC1
occurs as a
result of any of the following conditions:
a. Falling edge of CE.
b. Falling edge of WE (CE active).
c. Transition on any address line (CE
active).
d. Transition on any data line (CE, and WE
active).
The device automatically powers down
from
I
CC1
to
I
CC2
after
t
PD
has elapsed from
any of the prior conditions. This means that
power dissipation is dependent on only
cycle rate, and is not on Chip Select pulse
width.
+5 V
OUTPUT
R
2
255
Ω
R
1
480
Ω
20. At any given temperature and voltage
condition, output disable time is less than
output enable time for any given device.
21. Transition is measured ±200 mV from
steady state voltage with specified loading
in Fig. 1b. This parameter is sampled and
not 100% tested.
22. All address timings are referenced from
the last valid address line to the first transi-
tioning address line.
23. CE or WE must be inactive during ad-
dress transitions.
24. This product is a very high speed device
and care must be taken during testing in
order to realize valid test information. In-
adequate attention to setups and proce-
dures can cause a good part to be rejected as
faulty. Long high inductance leads that
cause supply bounce must be avoided by
bringing the
V
CC
and ground planes di-
rectly up to the contactor fingers. A 0.01 µF
high frequency capacitor is also required
between
V
CC
and ground. To avoid signal
reflections, proper terminations must be
used.
1
2
3
4
5
6
7
F
IGURE
1a.
R
1
480
Ω
+5 V
OUTPUT
8
30 pF
R
2
255
Ω
INCLUDING
JIG AND
SCOPE
9
10
F
IGURE
1b.
11
INCLUDING
JIG AND
SCOPE
5 pF
F
IGURE
2.
+3.0 V
10%
90%
90%
10%
<3 ns
GND
<3 ns
256K Static RAMs
4-7
03/05/95–LDS.197-F
DSP and ARM Processors
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