DF2B7M3SC
ESD Protection Diodes
Silicon Epitaxial Planar
DF2B7M3SC
1. Applications
•
ESD Protection
This product is designed for protection against electrostatic discharge (ESD) and is not intended for any other
purpose, including, but not limited to, voltage regulation.
Note:
2. Packaging and Internal Circuit
1: Pin 1
2: Pin 2
SC2
25
3. Absolute Maximum Ratings (Note) (Unless otherwise specified, T
a
= 25
)
Characteristics
Electrostatic discharge voltage (IEC61000-4-2)(Contact)
Junction temperature
Storage temperature
Symbol
V
ESD
T
j
T
stg
Rating
±8
150
-55 to 150
Unit
kV
Note:
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
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2013-08-03
Rev.1.0
DF2B7M3SC
4. Electrical Characteristics (Unless otherwise specified, T
a
= 25
)
25
V
RWM
: Working peak reverse
voltage
V
BR
: Reverse breakdown voltage
I
BR
: Reverse breakdown current
I
R
: Reverse current
V
C
: Clamp voltage
I
PP
: Peak pulse current
R
DYN
: Dynamic resistance
Fig. 4.1 Definitions of Electrical Characteristics
Characteristics
Working peak reverse voltage
Reverse breakdown voltage
Reverse current
Clamp voltage
Dynamic resistance
Total capacitance
Total capacitance
Symbol
V
RWM
V
BR
I
R
V
C
R
DYN
C
t
C
t
Note
I
BR
= 1 mA
Test Condition
Min
6
Typ.
13.5
1.4
0.1
0.1
Max
5
0.5
0.2
Unit
V
V
µA
V
Ω
pF
pF
V
RWM
= 5 V
(Note 1) I
PP
= 1 A
(Note 2)
(Note 3) V
R
= 0 V, f = 1 MHz
(Note 3) V
R
= 0 V, f = 5 GHz
Note 1: Based on IEC61000-4-5 8/20
µs
pulse.
Note 2: TLP parameter: Z0 = 50
Ω,
tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns,
extraction of dynamic resistance using a least-squares fit of TLP characteristics at I
PP
between 3 A to 8 A.
Note 3: Guaranteed by design.
5. Guaranteed ESD Protection (Note)
Test Condition
IEC61000-4-2 (Contact discharge)
ESD Protection
±8
kV
Note:
Criterion: No damage to devices.
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Rev.1.0
DF2B7M3SC
6. Marking
Fig. 6.1 Marking
7. Land Pattern Dimensions (for reference only)
Fig. 7.1 Land Pattern Dimensions (Unit: mm)
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Rev.1.0
DF2B7M3SC
8. Characteristics Curves (Note)
Fig. 8.1 I - V
Fig. 8.2 I
R
- V
R
Fig. 8.3 C
t
- V
R
Note:
Fig. 8.4 C
t
- f
The above characteristics curves are presented for reference only and not guaranteed by production test,
unless otherwise noted.
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2013-08-03
Rev.1.0
DF2B7M3SC
9. Clamp Voltage V
C
- Peak Pulse Current (I
PP
) (Note)
Fig. 9.1 V
C
- I
PP
Note:
Fig. 9.2 Based on IEC61000-4-5 8/20
µ
s pulse.
The above characteristics curves are presented for reference only and not guaranteed by production test,
unless otherwise noted.
10. Insertion Loss (S21) (Note)
Fig. 10.1 S21 - f
Note:
The above characteristics curves are presented for reference only and not guaranteed by production test,
unless otherwise noted.
5
2013-08-03
Rev.1.0
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