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VG36648041CT-8

Description
Synchronous DRAM, 8MX8, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP-54
Categorystorage    storage   
File Size1MB，70 Pages
ManufacturerVanguard International Semiconductor Corporation
Websitehttp://www.vis.com.tw/
Download Datasheet Parametric Compare View All

VG36648041CT-8 Overview

Synchronous DRAM, 8MX8, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP-54

VG36648041CT-8 Parametric

Parameter NameAttribute value
MakerVanguard International Semiconductor Corporation
Parts packaging codeTSOP
package instructionTSOP2,
Contacts54
Reach Compliance Codeunknown
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time6 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-PDSO-G54
length22.22 mm
memory density67108864 bit
Memory IC TypeSYNCHRONOUS DRAM
memory width8
Number of functions1
Number of ports1
Number of terminals54
word count8388608 words
character code8000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize8MX8
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Certification statusNot Qualified
Maximum seat height1.2 mm
self refreshYES
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationDUAL
width10.16 mm

VG36648041CT-8 Preview

VIS
Description
Preliminary
VG36648041CT
CMOS Synchronous Dynamic RAM
The device is CMOS Synchronous Dynamic RAM organized as 2,097,152 - word x 8-bit x 4-bank. it is
fabricated with an advanced submicron CMOS technology and designed to operate from a singly 3.3V only
power supply. It is packaged in JEDEC standard pinout and standard plastic TSOP package.
Features
• Single 3.3V (
±
0.3V ) power supply
• High speed clock cycle time : 7/8ns
• Fully synchronous with all signals referenced to a positive clock edge
• Programmable CAS Iatency (2,3)
• Programmable burst length (1,2,4,8,& Full page)
• Programmable wrap sequence (Sequential/Interleave)
• Automatic precharge and controlled precharge
• Auto refresh and self refresh modes
• Quad Internal banks controlled by A12 & A13 (Bank select)
• Each Bank can operate simultaneously and independently
• LVTTL compatible I/O interface
• Random column access in every cycle
• X8 organization
• Input/Output controlled by DQM
• 4,096 refresh cycles/64ms
• Burst termination by burst stop and precharge command
• Burst read/single write option
The information shown is subject to change without notice.
Document : 1G5-0153
Rev.1
Page 1
VIS
Pin Configuration
V
DD
DQ0
V
DDQ
NC
DQ1
V
SSQ
NC
DQ2
V
DDQ
NC
DQ3
V
SSQ
NC
V
DD
NC
WE
CAS
RAS
CS
A13/BA0
A12/BA1
A
10
A
0
A
1
A
2
A
3
V
DD
Preliminary
VG36648041CT
CMOS Synchronous Dynamic RAM
VG36648041
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ7
V
SSQ
NC
DQ6
V
DDQ
NC
DQ5
V
SSQ
NC
DQ4
V
DDQ
NC
V
SS
NC
DQM
CLK
CKE
NC
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
Pin Description
VG36648041
Pin Name
A0 - A11
A12,A13
DQ0 ~ DQ7
RAS
CAS
WE
V
SS
V
DD
Function
Address inputs
Bank select
Data - in/data - out
Row address strobe
Column address strobe
Write enable
Ground
Power ( + 3.3V)
Pin Name
DQM
CLK
CKE
CS
V
DDQ
V
SSQ
Function
DQ Mask enable
Clock input
Clock enable
Chip select
Supply voltage for DQ
Ground for DQ
Document : 1G5-0153
Rev.1
Page 2
VIS
Block Diagram
CLK
CKE
Clock
Generator
Preliminary
VG36648041CT
CMOS Synchronous Dynamic RAM
Address
Mode
Register
Row Decoder
Row
Address
Buffer
&
Refresh
Counter
Bank D
Bank C
Bank B
Bank A
Command Decoder
Sense Amplifier
Control Logic
Column
Address
Buffer
&
Burst
Counter
Column Decoder &
Latch Circuit
Input & Output
Buffer
Latch Circuit
CS
RAS
CAS
WE
DQM
Data Control Circuit
DQ
Document : 1G5-0153
Rev.1
Page 3
VIS
Absolute Maximum D.C. Ratings
Parameter
Voltage on any pin relative to Vss
Supply voltage relative to Vss
Short circuit output current
Power dissipation
Operating temperature
Storage temperature
Preliminary
VG36648041CT
CMOS Synchronous Dynamic RAM
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
I
OUT
P
D
T
OPT
T
STG
Value
-0.5 to + 4.6
-0.5 to + 4.6
50
1.0
0 to + 70
-55 to + 125
Unit
V
V
mA
W
°C
°C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
peumanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Maximum A.C. Operating Requirements for LVTTL Compatible
Parameter
Input High Voltage
Input Low Voltage
Symbol
V
IH
V
IL
Min
2.0
V
SSQ
-2.0
Max
V
DDQ
+ 2.0
0.8
Unit
V
V
Notes
2
2
Recommended DC Operating Conditions for LVTTL Compatible
Parameter
Supply Voltage
Input High Voltage, all inputs
Input Low Voltage, all inputs
Symbol
V
DD,
V
DDQ
V
IH
V
IL
Min
3.0
2.0
-0.3
Typ
3.3
-
-
Max
3.6
V
DD
+ 0.3
0.8
Unit
V
V
V
Capacitance
(Ta = 25°C, f = 1MHZ)
Parameter
Input capacitance (All input pins except CLK pin)
CLK pin
Data input/output capacitance
Symbol
C
in
C
CLK
C
I/O
Min
2.5
2.5
4.0
Typ
3.75
3.25
5.25
Max
5.0
4.0
6.5
Unit
pF
pF
pF
Notes
1
1
1
Notes : 1. Capacitance measured with effective capacitance measuring method.
2. The overshoot and undershoot voltage duration is
≤
3ns with no input clamp diodes.
Document : 1G5-0153
Rev.1
Page 4
VIS
Preliminary
VG36648041CT
CMOS Synchronous Dynamic RAM
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
VG36648041B
Parameter
Symbol
Test Conditions
-7
-8
Unit
Min Max Min Max
CL = 3
130
130
mA
Operating current
I
CC1
Burst length = 1
One bank active
CL = 2
130
130
t
RC
≤
t
RC(MIN.)
, Io = 0mA
Precharge standby
I
CC
2P CKE
≤
V
IH(MAX.)
t
CK
= 10ns
current in power
I
CC
2PS CKE
≤
V
down mode
IH(MAX.)
t
CK
=
∞
Precharge standby current I
CC
2N CKE
≥
V
IH(MIN.)
t
CK
= 10ns.
CKE
in Nonpower down mode
CS
CKE
≥
V
IH(MIN.)
Input signals are changed one
time during 2 CLK cycles.
I
CC
2NS
CKE
≥
V
CKE
V
, tCK =
∞
CLK
≤
V
IL(MAX.)
Input signals are stable.
CKE
IH(MIN.)
Notes
1
2
2
25
2
2
25
mA
mA
10
10
Active standby current in
power down mode
Active standby current in
Nonpower down mode
I
CC
3P
≤
V
IL(MAX.)
, t
CK
= 10ns
7
5
40
7
5
40
mA
I
CC
3PS CKE
I
CC
3N
≤
V
IL(MAX.)
, t
CK
=
∞
CKE
≥
V
IH(MAX.)
, t
CK
= 10ns
CKE
CS
CKE
≥
V
IH(MIN.)
Input signals are changed
one time during 2CLKs.
mA
I
CC
3NS CKE
CKE
≥
V
IH(MIN.)
t
CK
=
∞
CLE
≤
V
IL(MAX.)
Input signals are stable.
t
CK(MIN.)
, Io = 0mA
≥
V
CL = 3
CL = 2
20
20
Operating current
(Burst mode)
Refresh current
Self refresh current
Input leakage current
(Inputs)
Output leakage current
(I/O pins)
Output Low Voltage
Output High Voltage
I
CC4
I
CC5
I
CC6
I
LI
I
IL
V
OL
V
OH
t
CK
CKE
t
RC
All banks Active
170
135
220
1
-1
-1.5
1
1.5
0.4
2.4
2.4
-1
-1.5
170
120
200
1
1
1.5
0.4
mA
mA
mA
µA
µA
mA
mA
2
3
≥
t
RC(MIN.)
CKE
≤
0.2V
0
≤
V
IN
≤
V
DD(MAX)
Pins not under test = 0V
0
≤
V
OUT
≤
V
DD (MAX)
DQ# in Hi - Z., Dout disabled
I
OL
= 2mA
I
OH
= -2mA
4
4
Notes :
1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output
open. In addition to this, ICC1 is measured on condition that addresses are changed only one
time during t
CK(MIN.)
.
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output
open. In addition to this, ICC4 is measured on condition that addresses are changed only one
time during t
CK(MIN.)
.
3. ICC5 is measured on condition that addresses are changed only one time during t
CK(MIN.)
.
4. For LVTTL compatible, VG36648041.
Document : 1G5-0153
Rev.1
Page 5
More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

VG36648041CT-8 Related Products

VG36648041CT-8 VG36648041CT-7
Description Synchronous DRAM, 8MX8, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP-54 Synchronous DRAM, 8MX8, 6ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP-54
Maker Vanguard International Semiconductor Corporation Vanguard International Semiconductor Corporation
Parts packaging code TSOP TSOP
package instruction TSOP2, TSOP2,
Contacts 54 54
Reach Compliance Code unknown unknown
ECCN code EAR99 EAR99
access mode FOUR BANK PAGE BURST FOUR BANK PAGE BURST
Maximum access time 6 ns 6 ns
Other features AUTO/SELF REFRESH AUTO/SELF REFRESH
JESD-30 code R-PDSO-G54 R-PDSO-G54
length 22.22 mm 22.22 mm
memory density 67108864 bit 67108864 bit
Memory IC Type SYNCHRONOUS DRAM SYNCHRONOUS DRAM
memory width 8 8
Number of functions 1 1
Number of ports 1 1
Number of terminals 54 54
word count 8388608 words 8388608 words
character code 8000000 8000000
Operating mode SYNCHRONOUS SYNCHRONOUS
Maximum operating temperature 70 °C 70 °C
organize 8MX8 8MX8
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSOP2 TSOP2
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE
Certification status Not Qualified Not Qualified
Maximum seat height 1.2 mm 1.2 mm
self refresh YES YES
Maximum supply voltage (Vsup) 3.6 V 3.6 V
Minimum supply voltage (Vsup) 3 V 3 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V
surface mount YES YES
technology CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL
Terminal form GULL WING GULL WING
Terminal pitch 0.8 mm 0.8 mm
Terminal location DUAL DUAL
width 10.16 mm 10.16 mm

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Shortcut:   00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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