Datasheet
μ
PD44164182B
μ
PD44164362B
18M-BIT DDR II SRAM
2-WORD BURST OPERATION
Description
The
μ
PD44164182B is a 1,048,576-word by 18-bit and the
μ
PD44164362B is a 524,288-word by 36-bit
synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-
transistor memory cell.
The
μ
PD44164182B and
μ
PD44164362B integrate unique synchronous peripheral circuitry and a burst
counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K
and K#. These products are suitable for application which require synchronous operation, high speed, low
voltage, high density and wide bit configuration. These products are packaged in 165-pin PLASTIC BGA.
R10DS0014EJ0200
Rev.2.00
October 6, 2011
Features
•
1.8
±
0.1 V power supply
•
165-pin PLASTIC BGA (13 x 15)
•
HSTL interface
•
PLL circuitry for wide output data valid window and future frequency scaling
•
Pipelined double data rate operation
•
Common data input/output bus
•
Two-tick burst for low DDR transaction size
•
Two input clocks (K and K#) for precise DDR timing at clock rising edges only
•
Two output clocks (C and C#) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
•
Internally self-timed write control
•
Clock-stop capability. Normal operation is restored in 20
μ
s after clock is resumed.
•
User programmable impedance output (35 to 70
Ω)
•
Fast clock cycle time : 3.3 ns (300 MHz), 3.5 ns (287 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)
•
Simple control logic for easy depth expansion
•
JTAG 1149.1 compatible test access port
R10DS0014EJ0200 Rev.2.00
October 6, 2011
Page 1 of 34
μ
PD44164182B,
μ
PD44164362B
Ordering Information
Part No.
Organization
(word x bit)
1M x 18
Cycle
time
3.3ns
3.5ns
4.0ns
5.0ns
512K x 36
3.3ns
3.5ns
4.0ns
5.0ns
1M x 18
3.3ns
3.5ns
4.0ns
5.0ns
512K x 36
3.3ns
3.5ns
4.0ns
5.0ns
1M x 18
3.3ns
3.5ns
4.0ns
5.0ns
512K x 36
3.3ns
3.5ns
4.0ns
5.0ns
1M x 18
3.3ns
3.5ns
4.0ns
5.0ns
512K x 36
3.3ns
3.5ns
4.0ns
5.0ns
Clock
frequency
300MHz
287MHz
250MHz
200MHz
300MHz
287MHz
250MHz
200MHz
300MHz
287MHz
250MHz
200MHz
300MHz
287MHz
250MHz
200MHz
300MHz
287MHz
250MHz
200MHz
300MHz
287MHz
250MHz
200MHz
300MHz
287MHz
250MHz
200MHz
300MHz
287MHz
250MHz
200MHz
Ta =
−40
to 85°C
165-pin
PLASTIC BGA
(13 x 15)
Lead
Ta =
−40
to 85°C
165-pin
PLASTIC BGA
(13 x 15)
Lead-free
Ta = 0 to 70°C
165-pin
PLASTIC BGA
(13 x 15)
Lead
Operating Ambient
Temperature
Ta = 0 to 70°C
Package
165-pin
PLASTIC BGA
(13 x 15)
Lead-free
μ
PD44164182BF5-E33-EQ3-A
μ
PD44164182BF5-E35-EQ3-A
μ
PD44164182BF5-E40-EQ3-A
μ
PD44164182BF5-E50-EQ3-A
μ
PD44164362BF5-E33-EQ3-A
μ
PD44164362BF5-E35-EQ3-A
μ
PD44164362BF5-E40-EQ3-A
μ
PD44164362BF5-E50-EQ3-A
μ
PD44164182BF5-E33-EQ3
μ
PD44164182BF5-E35-EQ3
μ
PD44164182BF5-E40-EQ3
μ
PD44164182BF5-E50-EQ3
μ
PD44164362BF5-E33-EQ3
μ
PD44164362BF5-E35-EQ3
μ
PD44164362BF5-E40-EQ3
μ
PD44164362BF5-E50-EQ3
μ
PD44164182BF5-E33Y-EQ3-A
μ
PD44164182BF5-E35Y-EQ3-A
μ
PD44164182BF5-E40Y-EQ3-A
μ
PD44164182BF5-E50Y-EQ3-A
μ
PD44164362BF5-E33Y-EQ3-A
μ
PD44164362BF5-E35Y-EQ3-A
μ
PD44164362BF5-E40Y-EQ3-A
μ
PD44164362BF5-E50Y-EQ3-A
μ
PD44164182BF5-E33Y-EQ3
μ
PD44164182BF5-E35Y-EQ3
μ
PD44164182BF5-E40Y-EQ3
μ
PD44164182BF5-E50Y-EQ3
μ
PD44164362BF5-E33Y-EQ3
μ
PD44164362BF5-E35Y-EQ3
μ
PD44164362BF5-E40Y-EQ3
μ
PD44164362BF5-E50Y-EQ3
R10DS0014EJ0200 Rev.2.00
October 6, 2011
Page 2 of 34
μ
PD44164182B,
μ
PD44164362B
Pin Arrangement
165-pin PLASTIC BGA (13 x 15)
(Top View)
[
μ
PD44164182B]
1M x 18
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
/72M
DQ9
NC
NC
NC
DQ12
NC
V
REF
NC
NC
DQ15
NC
NC
NC
TCK
3
A
NC
NC
DQ10
DQ11
NC
DQ13
V
DD
Q
NC
DQ14
NC
NC
DQ16
DQ17
A
4
R, W#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
5
BW1#
NC/288M
6
K#
K
A0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C#
7
NC/144M
8
LD#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
A
10
V
SS
/36M
NC
DQ7
NC
NC
NC
NC
V
REF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
BW0#
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
A0, A
DQ0 to DQ17
LD#
R, W#
BW0#, BW1#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
Remarks 1.
2.
3.
: Address inputs
: Data inputs / outputs
: Synchronous load
: Read Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: PLL disable
TMS
TDI
TCK
TDO
V
REF
V
DD
V
DD
Q
V
SS
NC
NC/xxM
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
: Expansion address for xxMb
×××#
indicates active LOW.
Refer to
Package Dimensions
for the index mark.
2A, 7A, 10A and 5B are expansion addresses
: 10A for 36Mb
: 10A and 2A for 72Mb
: 10A, 2A and 7A for 144Mb
: 10A, 2A, 7A and 5B for 288Mb
2A and 10A of this product can also be used as NC.
R10DS0014EJ0200 Rev.2.00
October 6, 2011
Page 3 of 34
μ
PD44164182B,
μ
PD44164362B
Pin Arrangement
165-pin PLASTIC BGA (13 x 15)
(Top View)
[
μ
PD44164362B]
512K x 36
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
2
3
4
R, W#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
5
BW2#
BW3#
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K#
K
A0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C#
7
BW1#
BW0#
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
A
10
V
SS
/72M
11
CQ
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
V
SS
/144M NC/36M
DQ27
NC
DQ29
NC
DQ30
DQ31
V
REF
NC
NC
DQ33
NC
DQ35
NC
TCK
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
V
DD
Q
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
A
NC
DQ17
NC
DQ15
NC
NC
V
REF
DQ13
DQ12
NC
DQ11
NC
DQ9
TMS
A0, A
DQ0 to DQ35
LD#
R, W#
BW0# to BW3#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
Remarks 1.
2.
3.
: Address inputs
: Data inputs / outputs
: Synchronous load
: Read Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: PLL disable
TMS
TDI
TCK
TDO
V
REF
V
DD
V
DD
Q
V
SS
NC
NC/xxM
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
: Expansion address for xxMb
×××#
indicates active LOW.
Refer to
Package Dimensions
for the index mark.
2A, 3A and 10A are expansion addresses : 3A for 36Mb
: 3A and 10A for 72Mb
: 3A, 10A and 2A for 144Mb
2A and 10A of this product can also be used as NC.
R10DS0014EJ0200 Rev.2.00
October 6, 2011
Page 4 of 34
μ
PD44164182B,
μ
PD44164362B
Pin Description
(1/2)
Symbol
A0
A
Type
Input
Description
Synchronous Address Inputs: These inputs are registered and must meet the setup
and hold times around the rising edge of K. All transactions operate on a burst of two
words (one clock period of bus activity). A0 is used as the lowest order address bit
permitting a random starting address within the burst operation on x18 and x36
devices. These inputs are ignored when device is deselected, i.e., NOP (LD# =
HIGH).
Synchronous Data IOs: Input data must meet setup and hold times around the rising
edges of K and K#. Output data is synchronized to the respective C and C# data
clocks or to K and K# if C and C# are tied to HIGH.
x18 device uses DQ0 to DQ17.
x36 device uses DQ0 to DQ35.
Synchronous Load: This input is brought LOW when a bus cycle sequence is to be
defined. This definition includes address and read/write direction. All transactions
operate on a burst of 2 data (one clock period of bus activity).
Synchronous Read/Write Input: When LD# is LOW, this input designates the access
type (READ when R, W# is HIGH, WRITE when R, W# is LOW) for the loaded
address. R, W# must meet the setup and hold times around the rising edge of K.
Synchronous Byte Writes: When LOW these inputs cause their respective byte to be
registered and written during WRITE cycles. These signals must meet setup and hold
times around the rising edges of K and K# for each of the two rising edges comprising
the WRITE cycle. See
Pin Arrangement
for signal to data relationships.
x18 device uses BW0#, BW1#.
x36 device uses BW0# to BW3#.
See
Byte Write Operation
for relation between BWx# and Dxx.
Input Clock: This input clock pair registers address and control inputs on the rising
edge of K, and registers data on the rising edge of K and the rising edge of K#. K# is
ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and
hold times around the clock rising edges.
Output Clock: This clock pair provides a user controlled means of tuning device output
data. The rising edge of C# is used as the output timing reference for first output data.
The rising edge of C is used as the output reference for second output data. Ideally,
C# is 180 degrees out of phase with C. When use of K and K# as the reference
instead of C and C#, then fixed C and C# to HIGH. Operation cannot be guaranteed
unless C and C# are fixed to HIGH (i.e. toggle of C and C#)
DQ0 to DQxx
Input/Output
LD#
Input
R, W#
Input
BWx#
Input
K, K#
Input
C, C#
Input
R10DS0014EJ0200 Rev.2.00
October 6, 2011
Page 5 of 34
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