APA3163A
20W Stereo Digital Class-D Audio Power Amplifier with EQ and DRC
Features
General Description
The APA3163A is a digital input, stereo, high efficiency,
Class-D audio amplifier available in a TQFP7x7-48P
package.
The APA3163A accepts the digital serial audio data and
using the digital audio processor to convert the audio
data becomes the stereo Class-D output speaker
amplifier. This provides the seamless integration between
the codec and the speaker amplifier.
The APA3163A is a slave device receiving clocks from
external source, and the Class-D’ PWM switching fre-
s
quency is 352.8kHz for the sampling rate 44.1kHz or 384
kHz for sampling 48kHz, depend on the input signal’
s
sampling rate.
•
•
•
•
•
•
•
•
•
•
Operating Voltage: 8.0V~24V for PVDD
– 3.0V~3.6V for DVDD and AVDD
High Efficiency Class-D Operation Eliminate the
Need of Heatsinks
Digital Serial Audio Input (Stereo Output)
I
2
C Control Interface
Sampling Rate can Support from 32kHz to 192kHz
Separated Volume Control from 24dB to Mute
Soft Mute (50% Duty Cycle)
Shutdown and Mute Function
Thermal and Over-Current Protections with Auto-
Recovery
Space Saving Package TQFP7x7-48P
Lead Free and Green Devices Available
(RoHS Compliant)
•
Pin Configuration
48
PGND_AB
47
PGND_AB
46
OUT_B
45
PVDD_B
44
PVDD_B
43
BBS
42
CBS
41
PVDD_C
40
PVDD_C
39
OUT_C
38
PGND_CD
37
PGND_CD
Applications
•
LCD TV
Simplified Application Circuit
OUT_A
OUT_A 1
PVDD_A 2
PVDD_A 3
ABS 4
GDREG 5
NC 6
NC 7
TM 8
AVSS 9
PLL_LF
10
NC 11
NC 12
TOP VIEW
(APA3163A)
36 OUT_D
35 PVDD_D
34 PVDD_D
33 DBS
32 GDREG
31 DVREG
30 AGND
29 GND
28 DVSS
27 DVDD
26 TP3
25 RST
OUT_B
APA3163A
OUT_C
IC
Control
2
SDA
SCL
OUT_D
Right
Channel
Speaker
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright
©
ANPEC Electronics Corp.
Rev. A.1 - Mar., 2013
1
www.anpec.com.tw
AVDD 13
ERROR 14
MCLK 15
TP1 16
TP2 17
1V8_DV 18
SD 19
LRCK 20
SCLK 21
SDIN 22
SDA 23
SCL 24
Digital Audio
Source
MCLK
LRCLK
SCLK
SDIN
Left
Channel
Speaker
APA3163A
Ordering and Marking Information
APA3163A
Assembly Material
Handling Code
Temperature Range
Package Code
Package Code
QCA : TQFP7x7-48P
Operating Ambient Temperature Range
I : -40 to 85
o
C
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
XXXXX - Date Code
APA3163A QCA :
APA3163A
XXXXX
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings
Symbol
Supply Voltage (PVDD_X to PGND_XX)
Supply Voltage (DVDD to DVSS)
Supply Voltage (AVDD to AVSS)
Input Voltage (MCLK to AVSS)
(Note 1)
Rating
-0.3 to 26
-0.3 to 3.6
-0.3 to 3.6
-0.5 to AVDD+2.5
-0.5 to DVDD+2.5
-0.3 to +26
-0.3 to +31
-0.3 to +0.3
150
-65 to +150
260
Internally Limited
ο
Parameter
Unit
Input Voltage (SD, RST, LRCLK, SCLK, SDIN, SDA, SCL to DVSS)
Input Voltage (OUT_X to PGND_XX)
Input Voltage (XBS to PGND_XX)
Input Voltage (AVSS, DVSS, AGND to PGND_XX)
T
J
T
STG
T
SDR
P
D
Maximum Junction Temperature
Storage Temperature Range
Soldering Temperature Range, 10 seconds
Power Dissipation
V
C
C
ο
ο
C
W
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom-
mended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Thermal Characteristics
Symbol
θ
JA
Parameter
Junction-to-Ambient Resistance in Free Air
(Note 2)
TQFP7x7-48P
Typical Value
25
Unit
°C/W
Note 2:
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of TQFP7X7-48P is soldered directly on the PCB.
Note 3: The case temperature is measured at the center of the exposed pad on the underside of the TQFP7X7-48P package.
Copyright
©
ANPEC Electronics Corp.
Rev. A.1 - Mar., 2013
2
www.anpec.com.tw
APA3163A
Recommended Operating Conditions
Symbol
V
DD
PV
DD
V
IH
V
IL
T
A
T
J
R
L
L
O
Supply Voltage
Full Bridge Stage Supply Voltage (PVDD_X)
High Level Threshold Voltage
Low Level Threshold Voltage
Ambient Temperature Range
Junction Temperature Range
Speaker Resistance
Output Low Pass Filter Inductance
SD, MCLK, LRCLK, SCLK, SDIN,
SDA, SCL, RST
SD, MCLK, LRCLK, SCLK, SDIN,
SDA, SCL, RST
Parameter
Range
Min.
3
8
2
0
-40
-40
6
10
Max.
3.6
24
5
1
85
125
-
-
ο
Unit
V
C
Ω
µH
PWM Operating Conditions
Symbol
Parameter
Test Conditions
32 kHz Data Rate ±2%
f
S
Output Sample Rate
44.1k/88.2k/176.4 kHz Data Rate ±2%
48k/96k/192 kHz Data Rate ±2%
Value
256
352.8
384
kHz
Unit
PLL Input Parameters and External Filter Components
Symbol
f
MCLK
Parameter
MCLK Frequency
MCLK Duty Cycle
tr/tf
(MCLK)
Rise/Fall Time for MCLK
LRCLK Allowable Drift before
LRCLK Reset
External PLL Filter Capacitor C1
External PLL Filter Capacitor C2
External PLL Filter Resistor R
SMD 0603 Y5V
SMD 0603 Y5V
Test Conditions
APA3163A
Min.
2.8224
40
-
-
-
-
-
Typ.
-
50
-
-
47
4.7
470
Max.
24.576
60
5
4
-
-
-
Unit
MHz
%
ns
MCLKs
nF
Ω
Electrical Characteristics
T
A
=25 C, PV
DD
=18V, V
DD
=3.3V (AVDD and DVDD), R
L
=8Ω, BD Mode, f
S
=48kHz (unless otherwise noted)
Symbol
Parameter
Test Conditions
Min.
DC CHARACTERISTICS
I
DD
3.3V Supply Current (AVDD,
DVDD)
Full Bridge Stage Supply
Current
(PVDD_X)
Low Level Input Current
Normal Mode (No load)
Reset (No load)
Normal Mode (No load)
Reset (No load)
V
I
<V
IL
, V
DD
=3.6V (AVDD and
DVDD)
-
-
-
-
-
10
7.2
18
0.5
150
20
14.5
36
1
-
µA
mA
APA3163A
Typ.
Max.
Unit
ο
I
PVDD
I
IL
Copyright
©
ANPEC Electronics Corp.
Rev. A.1 - Mar., 2013
3
www.anpec.com.tw
APA3163A
Electrical Characteristics (Cont.)
T
A
=25 C, PV
DD
=18V, V
DD
=3.3V (AVDD and DVDD), R
L
=8Ω, BD Mode, f
S
=48kHz (unless otherwise noted)
Symbol
Parameter
Test Conditions
Min.
DC CHARACTERISTICS (CONT.)
I
IH
High Level Input Current
Drain to source resistance,LS
Drain to source resistance,HS
Thermal Protection Threshold
T
TP
η
R
OUT
Thermal Protection Threshold
Hysteresis
Efficiency
Internal Pull-Down Resistance at
Each OUT_X
Stereo, R
L
=8Ω, P
O
=18W
V
I
>V
IH
, V
DD
=3.6V (AVDD and
DVDD)
T
J
=25
o
C, includes metallization
resistance
T
J
=25
o
C, includes metallization
resistance
-
-
-
-
-
-
-
150
180
180
160
25
88
3
-
-
-
170
ο
ο
APA3163A
Typ.
Max.
Unit
µA
mΩ
mΩ
r
DS(ON)
-
-
-
C
%
kΩ
AC CHARACTERISTICS
THD+N=1%
f
in
=1kHz,
R
L
=8Ω
THD+N=1%
f
in
=1kHz,
R
L
=6Ω
THD+N=10%
f
in
=1kHz,
R
L
=8Ω
THD+N=10%
f
in
=1kHz,
R
L
=6Ω
PV
DD
=18V
PV
DD
=12V
PV
DD
=8V
PV
DD
=12V
PV
DD
=18V
PV
DD
=12V
PV
DD
=8V
PV
DD
=12V
PV
DD
=18V,
P
O
=1W
THD+N
Total Harmonic Distortion Plus
Noise
f
in
=1kHz,
R
L
=8Ω
PV
DD
=12V,
P
O
=1W
PV
DD
=8V,
P
O
=1W
Crosstalk
Att
Mute
Att
shutdown
S/N
V
n
Channel Separation
Mute Attenuation
Shutdown Attenuation
Signal to Noise Ratio
Noise Output Voltage
P
O
=0.25W, R
L
=8Ω, f
in
=1kHz
f
in
=1kHz, R
L
=8Ω, V
O
=1V
rms
f
in
=1kHz, R
L
=8Ω, V
O
=1V
rms
R
L
=8Ω, P
O
=16W, With
A-Weighting Filter (A
V
=0dB)
With A-Weighting Filter (A
V
=0dB)
14.5
6.5
2.9
8.1
-
-
-
-
-
-
-
-
-
-
-
-
16
7.2
3.2
9
20
9
4
11
0.06
0.13
0.2
-82
-70
-110
97
150
-
-
-
-
W
-
-
-
-
-
-
-
-
-
-
-
-
µV
rms
dB
%
P
O
Output Power
Copyright
©
ANPEC Electronics Corp.
Rev. A.1 - Mar., 2013
4
www.anpec.com.tw
APA3163A
Serial Audio Ports Slave Mode
Over recommended operating conditions (unless otherwise noted)
Symbol
f
SCLK
t
Setup1
t
Hold1
Parameter
Frequency, SCLK 32xf
S
, 48xf
S
,
64xf
S
Setup Time, LRCLK to SCLK
Rising Edge
Hold Time, LRCLK to SCLK
Rising Edge
Test Conditions
C
L
=30pF
APA3163A
Min.
1.024
10
10
Typ.
-
-
-
Max.
12.288
-
ns
-
Unit
MHz
Serial Audio Ports Slave Mode
Over recommended operating conditions (unless otherwise noted)
Symbol
t
Setup2
t
Hold
Parameter
Setup Time, SDIN to SCLK
Rising Edge
Hold Time, SDIN to SCLK Rising
Edge
LRCLK Frequency
LRCLK Duty Cycle
SCLK Duty Cycle
SCLK Rising Edges Between
LRCLK Riding Edges
t
(edge)
tr/tf
(SCLK/LRCLK)
Test Conditions
APA3163A
Min.
10
10
8K
40
40
32
-1/4
-
Typ.
-
-
48K
50
50
-
-
-
Max.
-
Unit
ns
-
48K
60
60
64
1/4
8
kHz
%
SCLK
edges
SCLK
period
ns
LRCLK Clock Edge With Respect
To The Falling Edge of SCLK
Rise/Fall Time for SCLK/LRCLK
Reset Timing
Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to “Rec-
ommended Use Model” section on usage of all terminals.
Symbol
t
p(RST)
t
d(12C_Ready)
Parameter
Pulse Duration, RST Active.
Time to Enable I
2
C
Test Conditions
Min.
No Load
100
-
APA3163A
Typ.
-
-
Max.
-
13.5
µs
ms
Unit
Copyright
©
ANPEC Electronics Corp.
Rev. A.1 - Mar., 2013
5
www.anpec.com.tw
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