8403601ZA datasheet, PDF - EEWORLD Datasheet

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8403601ZA: Description2KX8 STANDARD SRAM, 200ns, CQCC32, CERAMIC, CC-32; Categorystorage storage; File Size218KB，27 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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8403601ZA Overview

2KX8 STANDARD SRAM, 200ns, CQCC32, CERAMIC, CC-32

8403601ZA Parametric

Parameter Name	Attribute value
Maker	Renesas Electronics Corporation
Parts packaging code	QFN
package instruction	CERAMIC, CC-32
Contacts	32
Reach Compliance Code	unknown
ECCN code	3A001.A.2.C
Maximum access time	200 ns
Other features	TTL COMPATIBLE
JESD-30 code	R-CQCC-N32
length	13.97 mm
memory density	16384 bit
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of terminals	32
word count	2048 words
character code	2000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	2KX8
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QCCN
Package shape	RECTANGULAR
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	3.05 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	QUAD
width	11.43 mm

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REVISIONS

LTR

DESCRIPTION

Change to vendor similar part number for vendor CAGE number

61772 for devices 08KX, 09KX, 10KX, 11KX, 12KX, 13KX, 14KX,

15KX, and 16KX. Remove vendor CAGE number 61772 from devices

08YX, 09YX, 10YX, 11YX, 12YX, 13YX, 15YX, and 16YX. Change to

vendor similar part number for vendor CAGE number 65786 for

devices 09 and 11. Add vendor CAGE number 50088 to the drawing

as a source of supply for devices 04JX and 05JX. Add vendor CAGE

number 65896 to the drawing as a source of supply for devices 15 and

16. Removed 4.3.3 from drawing. Editorial changes throughout.

Added provisions for the addition of QD certified parts to drawing.

Updated boilerplate. Added CAGE OC7V7 as supplier. - ksr

DATE (YR-MO-DA)

92-04-27

APPROVED

M. A. Frye

00-09-27

Raymond Monnin

THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED

CURRENT CAGE CODE 67268

REV

SHEET

REV

SHEET

REV STATUS

OF SHEETS

PMIC N/A

REV

SHEET

PREPARED BY

James E. Jamison

STANDARD

MICROCIRCUIT

DRAWING

CHECKED BY

Ray Monnin

APPROVED BY

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43216

http://www.dscc.dla.mil

THIS DRAWING IS

AVAILABLE

FOR USE BY ALL

DEPARTMENTS

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE

Don Cool

DRAWING APPROVAL DATE

84 – 08 - 24

MICROCIRCUITS, MEMORY,

DIGITAL, CMOS, 16K

(2048 X 8) BIT STATIC RAM,

MONOLITHIC SILICON

SIZE

SHEET

CAGE CODE

AMSC N/A

REVISION LEVEL

14933

1 OF

84036

DSCC FORM 2233

APR 97

DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

5962-E173-00

2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the tex t

of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a

specific exemption has been obtained.

3. REQUIREMENTS

3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-

JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer

Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-

38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity

approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make

modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These

modifications shall not affect the PIN as described herein. A "Q" or "QML" certification mark in accordance with MIL-PRF-

38535 is required to identify when the QML flow option is used. This drawing has been modified to allow the manufacturer to

use the alternate die/fabrication requirements of paragraph A.3.2.2 of MIL-PRF-38535 or alternative approved by the Qualifying

Activity.

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as

specified in MIL-PRF-38535, appendix A and herein.

3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein and figure 1.

3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.

3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 3.

3.2.4 Logic diagram(s). The logic diagram(s) shall be as specified on figure 4.

3.2.5 Die overcoat. Polyimide and silicone coatings are allowable as an overcoat on the die for alpha particle protection

only. Each coated microcircuit inspection lot (see inspection lot as defined in MIL-PRF-38535) shall be subjected to and pass

the internal moisture content test at 5000 ppm (see method 1018 of MIL-STD-883). The frequency of the internal water vapor

testing shall not be decreased unless approved by the preparing activity for class M. The TRB will ascertain the requirements

as provided by MIL-PRF-38535 for classes Q and V. Samples may be pulled any time after seal.

3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are

as specified in table I and shall apply over the full (case or ambient) operating temperature range.

3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical

tests for each subgroup are described in table I.

3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN

listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked as listed in MIL-HDBK-103 (see 6.6 herein). For

packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the

option of not marking the "5962-" on the device.

3.5.1 Certification/compliance mark. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535,

Appendix A. For Class Q product built in accordance with A.3.2.2 of MIL-PRF-38535 or other alternative approved by the

Qualifying Activity, the "QD" certification mark shall be used in place of the "QML" or "Q" certification mark.

3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an

approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to

listing as an approved source of supply shall affirm that the manufacturer's product meets the requirements of MIL-PRF-

38535, appendix A and the requirements herein.

3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided

with each lot of microcircuits delivered to this drawing.

3.8 Notification of change. Notification of change to DSCC-VA shall be required in accordance with MIL-PRF-38535,

appendix A.

3.9 Verification and review. DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's

facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the

reviewer.

STANDARD

MICROCIRCUIT DRAWING

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43216-5000

DSCC FORM 2234

APR 97

SIZE

REVISION LEVEL

84036

SHEET

8403601ZA Related Products

	8403601ZA	8403607JA	8403607ZA	8403601JA
Description	2KX8 STANDARD SRAM, 200ns, CQCC32, CERAMIC, CC-32	2KX8 STANDARD SRAM, 120ns, CDIP24, CERAMIC, DIP-24	2KX8 STANDARD SRAM, 120ns, CQCC32, CERAMIC, CC-32	2KX8 STANDARD SRAM, 200ns, CDIP24, CERAMIC, DIP-24
Maker	Renesas Electronics Corporation	Renesas Electronics Corporation	Renesas Electronics Corporation	Renesas Electronics Corporation
Parts packaging code	QFN	DIP	QFJ	DIP
package instruction	CERAMIC, CC-32	CERAMIC, DIP-24	CERAMIC, LCC-32	CERAMIC, DIP-24
Contacts	32	24	32	24
Reach Compliance Code	unknown	not_compliant	unknown	not_compliant
ECCN code	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C
Maximum access time	200 ns	120 ns	120 ns	200 ns
Other features	TTL COMPATIBLE	TTL COMPATIBLE	TTL COMPATIBLE	TTL COMPATIBLE
JESD-30 code	R-CQCC-N32	R-GDIP-T24	R-CQCC-N32	R-GDIP-T24
memory density	16384 bit	16384 bit	16384 bit	16384 bit
Memory IC Type	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM
memory width	8	8	8	8
Number of functions	1	1	1	1
Number of terminals	32	24	32	24
word count	2048 words	2048 words	2048 words	2048 words
character code	2000	2000	2000	2000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C
organize	2KX8	2KX8	2KX8	2KX8
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, GLASS-SEALED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, GLASS-SEALED
encapsulated code	QCCN	DIP	QCCN	DIP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	CHIP CARRIER	IN-LINE	CHIP CARRIER	IN-LINE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	3.05 mm	5.72 mm	3.05 mm	5.72 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V
surface mount	YES	NO	YES	NO
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY
Terminal form	NO LEAD	THROUGH-HOLE	NO LEAD	THROUGH-HOLE
Terminal pitch	1.27 mm	2.54 mm	1.27 mm	2.54 mm
Terminal location	QUAD	DUAL	QUAD	DUAL
width	11.43 mm	15.24 mm	11.43 mm	15.24 mm

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