1. GENERAL DESCRIPTION ..................................................................................................................................................1
1.1 MAJOR FEATURES.......................................................................................................................................................1
1.2 COMPARISON OF PCI 9060 AND PCI 9060SD ...........................................................................................................2
2. BUS OPERATION ...............................................................................................................................................................3
2.1 PCI BUS CYCLES..........................................................................................................................................................3
2.2 LOCAL BUS CYCLES ....................................................................................................................................................3
2.2.1 Local Bus Slave .......................................................................................................................................................3
2.2.2 Local Bus Master .....................................................................................................................................................3
2.2.2.1 Ready/Wait State Control................................................................................................................................................... 3
2.2.2.3 Recovery States ................................................................................................................................................................. 4
2.2.2.4 Local Bus Read Accesses.................................................................................................................................................. 4
2.2.2.5 Local Bus Write Accesses.................................................................................................................................................. 5
2.2.2.6 Direct Slave Write Access to 8- and 16-bit bus.................................................................................................................. 5
2.2.2.7 Local Bus Data Parity......................................................................................................................................................... 5
2.2.2.8 Local Bus Little/Big Endian................................................................................................................................................. 5
3.1.1 PCI Bus Input RST# ................................................................................................................................................7
3.1.2 Local Bus Input LRESETi# ......................................................................................................................................7
3.1.3 Local Bus Output LRESETo# ..................................................................................................................................7
3.3.1 Short EEPROM Load...............................................................................................................................................7
3.3.2 Long EEPROM Load ...............................................................................................................................................8
3.3.3 Extra Long EEPROM Load....................................................................................................................................10
3.3.5 PCI Bus Access to Internal Registers....................................................................................................................11
3.3.6 Local Bus Access to Internal Registers .................................................................................................................11
3.4 DIRECT DATA TRANSFER MODES...........................................................................................................................12
3.4.1 Direct Bus Master Operation .................................................................................................................................12
3.4.2 Direct Slave Operation (PCI Master to Local Bus Access)....................................................................................12
3.4.2.1 PCI to Local Address Mapping ......................................................................................................................................... 13
3.4.2.1.1 Local Bus Initialization Software................................................................................................................................ 13
3.4.2.2 Direct Slave Lock ............................................................................................................................................................. 15
3.4.3 Direct Slave Priority ...............................................................................................................................................15
3.5.3 DMA Data Transfers ..............................................................................................................................................18
3.5.3.1 Local to PCI Bus DMA Transfer ....................................................................................................................................... 18
3.5.3.2 PCI to Local Bus DMA Transfer ....................................................................................................................................... 19
3.5.7.1 End Of Transfer (EOT1#) Input ........................................................................................................................................ 20
3.5.7.2 Local Latency and Pause Timers ..................................................................................................................................... 20
3.9.1.1 Local to PCI Doorbell Interrupt ......................................................................................................................................... 20
3.9.1.2 Local Interrupt Input ......................................................................................................................................................... 21
3.9.2 Local Interrupts (LINTo#).......................................................................................................................................21
3.9.2.1 PCI to Local Doorbell Interrupt ......................................................................................................................................... 21
3.9.2.2 Built-In Self Test Interrupt (BIST) ..................................................................................................................................... 21
3.9.4 Local LSERR# (Local NMI)....................................................................................................................................22
4.3 LOCAL CONFIGURATION REGISTERS ....................................................................................................................32
4.3.1 Local Address Space 0 Range Register for PCI to Local Bus (PCI 00h) (LOC 80h) ............................................32
4.3.2 Local Address Space 0 Local Base Address (Remap) Register for PCI to Local Bus (PCI 04h) (LOC 84h)........32
4.3.3 Local Arbitration Register (PCI 08h) (LOC 88h) ....................................................................................................33
4.4.8 EEPROM Control, PCI Command Codes, User I/O Control, Init Control Register (PCI 6Ch) (LOC ECh)............41
4.4.9 PCI Configuration ID Register (PCI 70h) (LOC F0h) .............................................................................................41
4.5 LOCAL DMA REGISTERS...........................................................................................................................................42
6. ELECTRICAL AND TIMING SPECIFICATIONS...............................................................................................................58
8.1 LIST OF TIMING DIAGRAMS ......................................................................................................................................64
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