PCI 9060
December, 1995
PCI Bus Master Interface Chip for
VERSION 1.2
Adapters and Embedded Systems
________________________________________________________________________________
Features
General Description _______________
The PCI9060 provides a compact high performance PCI
bus master interface for adapter boards and embedded
systems. The chip’s local bus follows the protocol of the
Intel i960® microprocessor family.
The PCI9060 provides two independent bi-directional
DMA channels with bi-directional FIFOs supporting zero
wait-state burst transfers between host and local
memory. Each channel also supports full data chaining
modes which allows concurrent operations. The chip
also contains a bi-directional FIFO for efficient slave
access. In addition, another bi-directional FIFO ensures
high speed Direct Bus Master transfers.
The PCI9060 also allows the local processor and other
intelligent controllers to perform direct bus master
transfers on the PCI bus. As an option, the PCI9060 can
enable the local processor to configure other PCI devices
in the system.
•
•
•
•
•
•
•
•
PCI Bus Master Interface supporting adapters and
embedded systems
Two independent DMA channels for local bus
memory to/from PCI host bus data transfers
Four bi-directional FIFOs for zero wait-state burst
operation; one for each DMA channel, one for Direct
Master interface and one for slave interface
PCI Bus Master transfers up to 132 MBytes/sec
Supports both multiplexed and non-multiplexed local
buses, 32, 16 or 8 bit. May connect directly to Intel
i960®Cx, Hx, Jx, Kx and Sx processors
Local bus can run asynchronously to the PCI clock.
Eight 32 bit mailbox and two 32 bit doorbell registers
Low power CMOS in 208 Pin Plastic QFP Package
________________________________________________________________________________
Figure 1. Typical Adapter or Embedded System Block Diagram
________________________________________________________________________________
©
PLX Technology, Inc., 1995
PLX Technology, Inc., 625 Clyde Avenue, Mountain View, CA 94043 (415) 960-0448 FAX (415) 960-0479
Products and Company names are trademarks/registered trademarks of their respective holders
TABLE OF CONTENTS
________________________________________________________________________________
TABLE OF CONTENTS
1. SECTION 1 - PCI 9060 GENERAL DESCRIPTION ..................................................................................................... 6
2. SECTION 2 - BUS OPERATION ................................................................................................................................. 7
2.1 PCI BUS CYCLES...................................................................................................................................................... 7
2.1.1 PCI Target Command Codes ............................................................................................................................... 7
2.1.2 PCI Master Command Codes............................................................................................................................... 7
2.1.2.1 DMA Master Command Codes........................................................................................................................................ 7
2.1.2.2 Direct Local to PCI Command Codes.............................................................................................................................. 7
2.2 LOCAL BUS CYCLES ................................................................................................................................................ 8
2.2.1 Local Bus Slave................................................................................................................................................... 8
2.2.2 Local Bus Master ................................................................................................................................................. 8
2.2.2.1 Ready/Wait State Control ............................................................................................................................................... 8
2.2.2.2 Burst Mode and Continuous Burst Mode (BTERM “Burst Terminate” mode) .................................................................... 8
2.2.2.3 Recovery States ............................................................................................................................................................ 8
2.2.2.4 Local Bus Read Accesses............................................................................................................................................... 9
2.2.2.5 Local Bus Write Accesses............................................................................................................................................... 9
2.2.2.6 Direct Slave Write Access to 8 and 16 bit bus ................................................................................................................. 9
2.2.2.7 Local Bus Data Parity ..................................................................................................................................................... 9
3. SECTION 3 - FUNCTIONAL DESCRIPTION............................................................................................................. 10
3.1 PCI 9060 I
NITIALIZATION
............................................................................................................................................ 10
3.2 RESET..................................................................................................................................................................... 10
3.2.1 PCI Bus Input RST#........................................................................................................................................... 10
3.2.2 Local Bus Input LRESETi#................................................................................................................................. 10
3.2.3 Local Bus Output LRESETo#............................................................................................................................. 10
3.2.4 Software Reset .................................................................................................................................................. 10
3.3 EEPROM ................................................................................................................................................................. 11
3.4 I
NTERNAL
R
EGISTER
A
CCESS
....................................................................................................................................... 13
3.4.1 PCI Bus Access to Internal Registers ................................................................................................................. 13
3.4.2 Local Bus Access to Internal Registers............................................................................................................... 14
3.5 D
IRECT
D
ATA
T
RANSFER
M
ODES
................................................................................................................................. 15
3.5.1 Direct Bus Master Operation (Local Master to PCI Bus Access) ......................................................................... 15
3.5.2 Direct Slave Operation (PCI Master to Local Bus Access)................................................................................. 18
3.5.2.1 PCI to Local Address Mapping...................................................................................................................................... 18
3.5.2.2 Deadlock and BREQo ................................................................................................................................................... 20
3.5.3 Direct Slave Priority ........................................................................................................................................... 21
3.6 DMA O
PERATION
....................................................................................................................................................... 22
3.6.1 Non-Chaining Mode DMA .................................................................................................................................. 22
3.6.2 Chaining Mode DMA.......................................................................................................................................... 23
3.6.3 DMA Data Transfers .......................................................................................................................................... 24
3.6.3.1 Local to PCI Bus DMA Transfer .................................................................................................................................... 24
3.6.3.2 PCI to Local Bus DMA Transfer .................................................................................................................................... 25
3.6.3.3 Unaligned Transfers...................................................................................................................................................... 26
3.6.4 Demand Mode DMA .......................................................................................................................................... 26
3.6.5 DMA Priority ...................................................................................................................................................... 26
3.6.6 DMA Arbitration ................................................................................................................................................. 26
3.6.6.1 Local Latency and Pause Timers .................................................................................................................................. 26
3.7 BREQ
INPUT
. ............................................................................................................................................................ 26
3.8 D
OORBELL
R
EGISTERS
................................................................................................................................................ 26
3.9 M
AILBOX
R
EGISTERS
.................................................................................................................................................. 27
3.10 I
NTERRUPTS
............................................................................................................................................................. 27
3.10.1 PCI Interrupts (INTA#) ..................................................................................................................................... 27
3.10.1.1 Doorbell Interrupt ........................................................................................................................................................ 27
3.10.1.2 Local Interrupt Input.................................................................................................................................................... 27
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Page - 2 -
Version 1.2
Section B
PCI9060
TABLE OF CONTENTS
________________________________________________________________________________
3.10.1.3 Master/Target Abort Interrupt ...................................................................................................................................... 27
3.10.2 Local Interrupts (LINTo#) ................................................................................................................................. 28
3.10.2.1 Doorbell Interrupt ........................................................................................................................................................ 28
3.10.2.2 Built In Self Test Interrupt (BIST) ................................................................................................................................ 28
3.10.2.3 DMA Channel 0/Channel 1 Interrupts .......................................................................................................................... 28
3.10.3 PCI SERR# (PCI NMI) .................................................................................................................................... 28
3.10.4 Local LSERR# (Local NMI) ............................................................................................................................ 29
4. SECTION 4 - REGISTERS ....................................................................................................................................... 30
4.1 R
EGISTER
A
DDRESS
M
APPING
..................................................................................................................................... 30
4.2 PCI C
ONFIGURATION
R
EGISTERS
................................................................................................................................. 32
4.2.1 PCI Configuration ID Register (Offset 00h) ........................................................................................................ 33
4.2.2 PCI Command Register (Offset 04h).................................................................................................................. 33
4.2.3 PCI Status Register (Offset 06h)........................................................................................................................ 34
4.2.4 PCI Revision ID Register (Offset 08h)................................................................................................................ 34
4.2.5 PCI Class Code Register (Offset 09 - 0Bh) ........................................................................................................ 35
4.2.6 PCI Cache Line Size Register (Offset 0Ch)........................................................................................................ 35
4.2.7 PCI Latency Timer Register (Offset 0Dh)........................................................................................................... 35
4.2.8 PCI Header Type Register (Offset 0Eh) ............................................................................................................. 35
4.2.9 PCI Built-In Self Test (BIST) Register (PCI Offset 0Fh)...................................................................................... 36
4.2.10 PCI Base Address Register for Memory Access to Runtime Registers (Offset 10h).......................................... 36
4.2.11 PCI Base Address Register for I/O Access to Runtime Registers(Offset 14h)................................................... 37
4.2.12 PCI Base Address Register for Memory Access to Local Address Space 0 (Offset 18h)................................... 37
4.2.13 PCI Base Address Register (Offset 1Ch).......................................................................................................... 37
4.2.14 PCI Base Address Register (Offset 20h) .......................................................................................................... 38
4.2.15 PCI Base Address Register (Offset 24h) .......................................................................................................... 38
4.2.16 PCI Base Address Register (Offset 28h) .......................................................................................................... 38
4.2.17 PCI Base Address Register (Offset 2Ch).......................................................................................................... 38
4.2.18 PCI Expansion ROM Base Register (Offset 30h).............................................................................................. 39
4.2.19 PCI Interrupt Line Register (Offset 3Ch)........................................................................................................... 39
4.2.20 PCI Interrupt Pin Register (Offset 3Dh) ............................................................................................................ 39
4.2.21 PCI Min_Gnt Register (Offset 3Eh) .................................................................................................................. 40
4.2.22 PCI Max_Lat Register (Offset 3Fh) .................................................................................................................. 40
4.3 L
OCAL
C
ONFIGURATION
R
EGISTERS
............................................................................................................................. 41
4.3.1 Local Address Space 0 Range Register for PCI to Local Bus (PCI 00h) (LOC 80h) ............................................ 41
4.3.2 Local Address Space 0 Local Base Address (Re-map) Register for PCI to Local Bus (PCI 04h) (LOC 84h)........ 41
4.3.3 Local Register (PCI 08h) (LOC 88h)................................................................................................................... 42
4.3.4 Local Register (PCI 0ch) (LOC 8ch) ................................................................................................................... 42
4.3.5 Local Expansion ROM Range Register for PCI to Local Bus (PCI 10h) (LOC 90h)............................................. 42
4.3.6 Local Expansion ROM Local Base Address (Re-map) register for PCI to Local Bus and BREQo Control (PCI
14h) (LOC 94h)........................................................................................................................................................... 42
4.3.7 Local Bus Region Descriptor for PCI to Local Accesses Register (PCI 18h) (LOC 98h) ...................................... 43
4.3.8 Local Range register for Direct Master to PCI (PCI 1Ch) (LOC 9Ch) .................................................................. 44
4.3.9 Local Bus Base Address register for Direct Master to PCI Memory (PCI 20h) (LOC A0h).................................. 44
4.3.10 Local Base Address for Direct Master to PCI IO/CFG Register (PCI 24h) (LOC A4h) ....................................... 44
4.3.11 PCI Base Address (Re-map) register for Direct Master to PCI (PCI 28h) (LOC A8h) ....................................... 45
4.3.12 PCI Configuration Address Register for Direct Master to PCI IO/CFG (PCI 2Ch) (LOC ACh) ........................... 45
4.4 S
HARED
R
UNTIME
R
EGISTERS
..................................................................................................................................... 46
4.4.1 Mailbox Register 0 (PCI 40h) (LOC C0h) ........................................................................................................... 46
4.4.2 Mailbox Register 1 (PCI 44h) (LOC C4h) ........................................................................................................... 46
4.4.3 Mailbox Register 2 (PCI 48h) (LOC C8h) ........................................................................................................... 46
4.4.4 Mailbox Register 3 (PCI 4Ch) (LOC CCh) .......................................................................................................... 46
4.4.5 Mailbox Register 4 (PCI 50h) (LOC D0h) ........................................................................................................... 47
4.4.6 Mailbox Register 5 (PCI 54h) (LOC D4h) ........................................................................................................... 47
4.4.7 Mailbox Register 6 (PCI 58h) (LOC D8h) ........................................................................................................... 47
4.4.8 Mailbox Register 7 (PCI 5Ch) (LOC DCh) .......................................................................................................... 47
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Page - 3 -
Version 1.2
Section B
PCI9060
TABLE OF CONTENTS
________________________________________________________________________________
4.4.9 PCI to Local Doorbell Register (PCI 60h) (LOC E0h) ......................................................................................... 48
4.4.10 Local to PCI Doorbell Register (PCI 64h) (LOC E4h)........................................................................................ 48
4.4.11 Interrupt Control/Status (PCI 68h) (LOC E8h) .................................................................................................. 49
4.4.12 EEPROM Control, PCI Command Codes, User I/O Control, Init Control Register (PCI 6Ch) (LOC ECh).......... 50
4.5 L
OCAL
DMA R
EGISTERS
............................................................................................................................................. 51
4.5.1 DMA Channel 0 Mode Register (LOC 100h)...................................................................................................... 51
4.5.2 DMA Channel 0 PCI Address Register (LOC 104h) ............................................................................................ 51
4.5.3 DMA Channel 0 Local Address Register (LOC 108h) ......................................................................................... 52
4.5.4 DMA Channel 0 Transfer Size (Bytes) Register (LOC 10Ch) ............................................................................. 52
4.5.5 DMA Channel 0 Descriptor Pointer Register (LOC 110h) ................................................................................... 52
4.5.6 DMA Channel 1 Mode Register (LOC 114h)....................................................................................................... 53
4.5.7 DMA Channel 1 PCI Data Address Register (LOC 118h).................................................................................... 53
4.5.8 DMA Channel 1 Local Data Address Register (LOC 11Ch)................................................................................. 54
4.5.9 DMA Channel 1 Transfer Size (Bytes) Register (LOC 120h)............................................................................... 54
4.5.10 DMA Channel 1 Descriptor Pointer Register (LOC 124h).................................................................................. 54
4.5.11 DMA Command/Status Register (LOC 128h) .................................................................................................. 55
4.5.12 DMA Arbitration Register 0 (LOC 12Ch)........................................................................................................... 55
4.5.13 DMA Arbitration Register 1 (LOC 130h) ........................................................................................................... 56
5. SECTION 5 - PIN DESCRIPTION.............................................................................................................................. 57
5.1 P
IN
S
UMMARY
............................................................................................................................................................ 57
6. SECTION 6 - ELECTRICAL AND TIMING SPECIFICATIONS .................................................................................. 69
7. SECTION 7 - PACKAGE MECHANICAL DIMENSIONS ............................................................................................ 71
7.1 P
ACKAGE
M
ECHANICAL
D
IMENSIONS
............................................................................................................................. 72
7.2 T
YPICAL
PCI B
US
M
ASTER
A
DAPTER
............................................................................................................................ 73
7.3 I960C
X
®
MODE PIN OUT ........................................................................................................................................ 74
7.4 I960J
X
®
MODE PIN OUT ......................................................................................................................................... 75
7.5 I960S
X
®
MODE PIN OUT ........................................................................................................................................ 76
8. SECTION 8- TIMING DIAGRAMS ............................................................................................................................. 77
8.1 L
IST OF
T
IMING
D
IAGRAMS
........................................................................................................................................... 77
REVISION HISTORY
Date
03/01/95
1.0
Revision
Comment
1. DEN# is an I/O pin in Jx mode. DEN# should be tied high if unused.
2. For
PCI9060 Rev 2A
parts or later, A PCI master can access the DMA registers by performing a Direct Slave
access to the local bus. The local address should be that of the desired DMA register.
3. Timing Diagram updates
Corrected typographical errors, Clarified specifications, and Updated Timing Diagrams.
08/15/95
1.1
________________________________________________________________________________
Page - 4 -
Version 1.2
Section B
PCI9060
TABLE OF CONTENTS
________________________________________________________________________________
12/12/95
1.2
A. Updates from Rev. 2 chip to Rev. 3 chip : In addition to correcting errata, PLX made changes to the PCI 9060
to improve performance, flexibility and ease of use. The Rev. 3 is also entirely pin and software compatible
with the Rev. 2.
1. Errata 1 through 13 from Rev. 2 chip were corrected.
2. Direct Slave Read FIFO = 8 Words (32 Bytes) vs. 4 in Rev. 2
Direct Slave Write FIFO = 8 Words (32 Bytes) vs. 4 in Rev. 2
The increase in FIFO depths requires no software or hardware changes. The only difference the user will
observe is an increase in Direct Slave throughput.
3. DMA registers may be accessed from PCI bus as well as local bus as described in Version 1.2 data sheet.
4. 0 ns hold time on all PCI signals.
5. Local pre-fetch can be disabled (PCI disconnect after 1 data read) Default state is pre-fetch enabled. To
disable address space 0 pre-fetch set bit 8, Table 29 to 1. To disable expansion ROM pre-fetch set bit 9,
Table 29 to 1.
6. Many users want to have an option of mapping the entire PCI address space to the local bus. To
accommodate this Rev. 3 acts as follows: If the PCI address space for Direct Master accesses overlaps the
128 byte space for the run time registers, an access to that 128 byte space will access the run-time registers.
No Direct Master access will occur in the run-time address space.
7. For the same reasons as in 6, if the PCI address space for Direct Slave accesses overlaps the space for the
run time registers, an access to that space will access the run-time registers. No Direct Slave access will
occur in the run-time address space.
8. LSERR# is driven high during reset (instead of driven low in Rev. 2), to avoid erroneous LSERR# assertion.
9. Most NC pins in Rev. 3 are driven and must not be connected. In the Rev. 2 chip, most of the NC pins are
floating.
10. In Rev. 2 BREQo was asserted if there was any data in the FIFO during a write and deadlock situation. In
Rev. 3, BREQo is asserted only if DM FIFO is full during a write and deadlock situation.
11. During Direct Slave reads, the 9060 gives up the local bus if BREQi is asserted or it’s internal local bus
latency timer expires. The individual data cycles still need to be completed.
12. The 9060 keeps the local bus until the entire Direct Slave write cycle is complete, not just when the write
FIFO is empty. The 9060 still gives up the local bus if BREQi is asserted or it’s internal local bus latency
timer expires.
B. Revised Local Bus Maximum Setup and Hold times. Refer to Section 6 for complete AC/DC Electrical
Characteristics.
Local Bus Maximum setup and hold time comparison(Version 1.1 vs. 1.2 data sheet).
Signal
ADS#
LAD
LD
RDYi#
BLAST#
LDP
BTERM#
BREQ
HOLDA
DREQ#
Version 1.1
setup time
4
4
4
4
4
4
4
4
4
4
Version 1.1
hold time
3
3
3
3
3
3
3
3
3
3
Version 1.2
setup time
9
3
7
9
6
4
5
N.A.
5
6
Version 1.2
hold time
1
N.A.
1
1
1
1
1
1
1
1
Local Bus Maximum T
VALID
(Version 1.1 vs. 1.2 data sheet)
Signal
USERo
BREQo
DACK[1:0]#
Version 1.1 T
VALID
13
18
18
(MAX) NSEC
Version 1.2 T
VALID
21
21
20
(MAX) NSEC
(WORST CASE)
(WORST CASE)
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Page - 5 -
Version 1.2
Section B
PCI9060
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