DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD3794
2700 PIXELS
×
3 COLOR CCD LINEAR IMAGE SENSOR
The
µ
PD3794 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to
electrical signal and has the function of color separation.
The
µ
PD3794 has 3 rows of 2700 pixels, and each row has a single-sided readout type of charge transfer register.
And it has reset feed-through level clamp circuits, a clamp pulse generation circuit, an RGB selector and voltage
amplifiers. Therefore, it is suitable for 300 dpi/A4 color image scanners, color facsimiles and so on.
FEATURES
• Valid photocell
• Line spacing
• Color filter
• Resolution
: 2700 pixels
×
3
: 32
µ
m (4 lines) Green line-Blue line, Blue line-Red line
: Primary colors (red, green and blue), pigment filter (with light resistance 10
7
lx•hour)
: 12 dot/mm A4 (210
×
297 mm) size (shorter side)
300 dpi US letter (8.5”
×
11”) size (shorter side)
• Drive clock level : CMOS output under 5 V operation
• Data rate
• Power supply
• On-chip circuits
: 4 MHz MAX.
: +12 V
: Reset feed-through level clamp circuits
Clamp pulse generation circuit
RGB selector
Voltage amplifiers
• Photocell's pitch : 8
µ
m
ORDERING INFORMATION
Part Number
Package
CCD linear image sensor 22-pin plastic DIP (400 mil)
µ
PD3794CY
The information in this document is subject to change without notice.
Document No.S13125EJ1V0DS00(1st edition)
Date published December 1997 N CP(K)
Printed in Japan
©
1997
µ
PD3794
BLOCK DIAGRAM
φ
1
14
SEL1 SEL2
22
20
V
OD
19
GND
2
GND
11
GND
15
S2699
······
Photocell
(Green)
S2700
D15
D64
D65
D66
D67
S1
S2
Transfer gate
CCD analog shift register
S2699
S2700
13
φ
TG1
(Green)
······
Photocell
(Blue)
D15
D64
D65
D66
D67
S1
S2
Transfer gate
V
OUT
1
CCD analog shift register
S2699
S2700
12
φ
TG2
(Blue)
······
Photocell
(Red)
D15
D64
D65
D66
D67
S1
S2
Transfer gate
CCD analog shift register
Clamp pulse
generator
10
φ
TG3
(Red)
3
9
φ
RB
φ
2
2
µ
PD3794
PIN CONFIGURATION (Top View)
CCD linear image sensor 22-pin plastic DIP (400 mil)
Output signal
V
OUT
1
22
SEL1
RGB select input 1
Ground
GND
2
21
NC
No connection
1
1
Reset gate clock
φ
RB
1
3
20
SEL2
RGB select input2
No connection
NC
4
19
V
OD
Output drain voltage
No connection
NC
5
18
NC
No connection
Blue
Red
No connection
NC
6
Green
17
NC
No connection
No connection
NC
7
16
NC
No connection
No connection
NC
8
15
GND
Ground
Shift register clock 2
φ
2
9
14
φ
1
Shift register clock 1
2700
2700
2700
Transfer gate clock 3
(for Red)
Ground
φ
TG3
10
13
φ
TG1
Transfer gate clock 1
(for Green)
Transfer gate clock 2
(for Blue)
GND
11
12
φ
TG2
PHOTOCELL STRUCTURE DIAGRAM
PHOTOCELL ARRAY STRUCTURE DIAGRAM
(Line spacing)
8
µ
m
Green photocell array
4 lines
(32
µ
m)
5
µ
m
3
µ
m
8
µ
m
8
µ
m
Blue photocell array
4 lines
(32
µ
m)
Channel stopper
8
µ
m
Red photocell array
Aluminum
shield
3
µ
PD3794
ABSOLUTE MAXIMUM RATINGS (T
A
= +25
°
C)
Parameter
Output drain voltage
Shift register clock voltage
Reset gate clock voltage
Transfer gate clock voltage
RGB select input voltage
Operating ambient temperature
Storage temperature
V
OD
V
φ
1
, V
φ
2
V
φ
RB
V
φ
TG1
to V
φ
TG3
V
SEL1
,V
SEL2
T
A
T
stg
Symbol
Ratings
–0.3 to +15
–0.3 to +8
–0.3 to +8
–0.3 to +8
–0.3 to +8
–25 to +60
–40 to +70
Unit
V
V
V
V
V
°C
°C
Caution
Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (T
A
= +25
°
C)
Parameter
Output drain voltage
Shift register clock high level
Shift register clock low level
Reset gate clock high level
Reset gate clock low level
Transfer gate clock high level
Transfer gate clock low level
RGB select input high level
RGB select input low level
Data rate
V
OD
V
φ
1H
, V
φ
2H
V
φ
1L
, V
φ
2L
V
φ
RBH
V
φ
RBL
V
φ
TG1H
to V
φ
TG3H
V
φ
TG1L
to V
φ
TG3L
V
SEL1H
, V
SEL2H
V
SEL1L
, V
SEL2L
f
φ
RB
Symbol
MIN.
11.4
4.5
–0.3
4.5
–0.3
4.5
–0.3
4.5
–0.3
–
TYP.
12.0
5.0
0
5.0
0
V
φ
1H
Note
0
5.0
0
1.0
MAX.
12.6
5.5
+0.5
5.5
+0.5
V
φ
1H
Note
+0.5
5.5
+0.5
4.0
Unit
V
V
V
V
V
V
V
V
V
MHz
Note
When Transfer gate clock high level (V
φ
TG1H
to V
φ
TG3H
) is higher than Shift register clock high level (V
φ
1H
),
Image lag can increase.
4
µ
PD3794
ELECTRICAL CHARACTERISTICS
T
A
= +25
°C,
V
OD
= 12 V, data rate (f
φ
RB
) = 1 MHz, storage time = 10 ms,
light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1mm), input signal clock = 5 V
p-p
Parameter
Saturation voltage
Saturation exposure
Red
Green
Blue
Photo response non-uniformity
Average dark signal
Dark signal non-uniformity
Power consumption
Output impedance
Response
Red
Green
Blue
Image lag
Offset level
Note1
Output fall delay time
Note2
Total transfer efficiency
Symbol
V
sat
SER
SEG
SEB
PRNU
ADS
DSNU
P
W
Z
O
R
R
R
G
R
B
IL
V
OS
t
d
TTE
Test Conditions
MIN.
2.0
TYP.
3.0
0.205
0.225
0.375
MAX.
Unit
V
lx•s
lx•s
lx•s
V
OUT
= 1.0 V
Light shielding
Light shielding
6
0.5
4.0
300
0.5
10.3
9.4
5.6
14.6
13.3
8.0
5.0
4.5
6.0
70
92
98
20
5.0
10.0
600
1
18.9
17.2
10.4
10.0
7.5
%
mV
mV
mW
kΩ
V/lx•s
V/lx•s
V/lx•s
%
V
ns
%
V
OUT
= 1.0 V
V
OUT
= 1.0 V
V
OUT
= 1.0 V,
data rate = 4 MHz
Response peak
Red
Green
Blue
630
540
460
DR1
DR2
V
sat
/DSNU
V
sat
/σ
Light shielding
Light shielding
–1000
–
750
3000
–300
1.0
+500
–
nm
nm
nm
times
times
mV
mV
Dynamic range
Reset feed-through noise
Note1
Random noise
RFTN
σ
Notes 1.
Refer to
TIMING CHART 2.
2.
When the fall time of
φ
1 (t1) is the TYP. value (refer to
TIMING CHART 2).
5
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