DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD3777
5400 PIXELS
×
3 COLOR CCD LINEAR IMAGE SENSOR
The
µ
PD3777 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical
signal and has the function of color separation.
The
µ
PD3777 has 3 rows of 5400 pixels, and each row has a double-sided readout type of charge transfer register. And
it has reset feed-through level clamp circuits, a clamp pulse generation circuit and voltage amplifiers. Therefore, it is
suitable for 600 dpi/A4 color image scanners, color facsimiles and so on.
FEATURES
•
Valid photocell
•
Photocell size
•
Line spacing
•
Color filter
•
Resolution
:
: 5400 pixels
×
3
: 5.25
×
5.25
µ
m
2
•
Photocell’s pitch : 5.25
µ
m
: 42
µ
m (8 lines) Red line - Green line, Green line - Blue line
: Primary colors (red, green and blue), pigment filter (with light resistance 10 lx•hour)
: 24 dot/mm A4 (210
×
297 mm) size (shorter side)
600 dpi US letter (8.5”
×
11”) size (shorter side)
7
•
Drive clock level : CMOS output under 5 V operation
•
Data rate
•
Power supply
•
On-chip circuits
:
:
: 4 MHz MAX.
: +12 V
: Reset feed-through level clamp circuits
Clamp pulse generation circuit
Voltage amplifiers
ORDERING INFORMATION
Part Number
Package
CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
µ
PD3777CY
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14583EJ1V0DS00 (1st edition)
Date Published December 1999 NS CP (K)
Printed in Japan
©
1999
S1
D14
D64
S2
D65
D66
S5399
Transfer gate
CCD analog shift register
CCD analog shift register
Transfer gate
S1
D14
D64
S2
D65
D66
S5399
S5400
S5400
V
OUT
1
(Blue)
Photocell
(Blue)
D67
V
OUT
2
(Green)
Transfer gate
CCD analog shift register
D67
S1
D14
D64
S2
D65
D66
S5399
Transfer gate
CCD analog shift register
Clamp pulse
generator
S5400
V
OUT
3
(Red)
........
Photocell
(Red)
D67
2
GND
2
11
14
GND
BLOCK DIAGRAM
φ
1
V
OD
φ
2L
19
17
CCD analog shift register
Transfer gate
........
13
φ
TG1
(Blue)
21
12
φ
TG2
(Green)
Data Sheet S14583EJ1V0DS00
22
........
Photocell
(Green)
CCD analog shift register
Transfer gate
10
φ
TG3
(Red)
1
3
4
9
φ
2
µ
PD3777
φ
RB
φ
1L
µ
PD3777
PIN CONFIGURATION (Top View)
CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
•
µ
PD3777CY
Output signal 3 (Red)
Ground
Reset gate clock
Last stage shift register clock 1
No connection
No connection
No connection
No connection
Shift register clock 2
Transfer gate clock 3
(for Red)
Ground
V
OUT
3
GND
1
2
22
21
V
OUT
2
V
OUT
1
NC
V
OD
NC
Output signal 2 (Green)
Output signal 1 (Blue)
No connection
Output drain voltage
No connection
Last stage shift register clock 2
No connection
No connection
Shift register clock 1
Transfer gate clock 1
(for Blue)
Transfer gate clock 2
(for Green)
1
1
φ
RB
φ
1L
NC
NC
NC
NC
3
4
5
6
1
20
19
18
17
16
15
14
13
12
Green
Blue
Red
φ
2L
NC
NC
7
8
9
10
11
φ
2
φ
1
φ
TG1
φ
TG2
5400
5400
GND
PHOTOCELL STRUCTURE DIAGRAM
PHOTOCELL ARRAY STRUCTURE DIAGRAM
(Line spacing)
5.25
µ
m
2.75
µ
m
2.5
µ
m
5400
φ
TG3
Blue photocell array
8 lines
(42
µ
m)
5.25
µ
m
5.25
µ
m
Channel stopper
Green photocell array
8 lines
(42
µ
m)
5.25
µ
m
Aluminum
shield
Red photocell array
Data Sheet S14583EJ1V0DS00
3
µ
PD3777
ABSOLUTE MAXIMUM RATINGS (T
A
= +25
°
C)
Parameter
Output drain voltage
Shift register clock voltage
Reset gate clock voltage
Transfer gate clock voltage
Operating ambient temperature
Storage temperature
V
OD
V
φ
1
, V
φ
2
, V
φ
1L
, V
φ
2L
V
φ
RB
V
φ
TG1
to V
φ
TG3
T
A
T
stg
Symbol
Ratings
−0.3
to +15
−0.3
to +8
−0.3
to +8
−0.3
to +8
−25
to +60
−40
to +70
Unit
V
V
V
V
°C
°C
Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (T
A
= +25
°
C)
Parameter
Output drain voltage
Shift register clock high level
Shift register clock low level
Reset gate clock high level
Reset gate clock low level
Transfer gate clock high level
Transfer gate clock low level
Data rate
V
OD
V
φ
1H
, V
φ
2H
, V
φ
1LH
, V
φ
2LH
V
φ
1L
, V
φ
2L
, V
φ
1LL
, V
φ
2LL
V
φ
RBH
V
φ
RBL
V
φ
TG1H
to V
φ
TG3H
V
φ
TG1L
to V
φ
TG3L
f
φ
RB
Symbol
MIN.
11.4
4.5
−0.3
4.5
−0.3
4.5
−0.3
−
TYP.
12.0
5.0
0
5.0
0
Note
V
φ
1H
MAX.
12.6
5.5
+0.5
5.5
+0.5
Note
V
φ
1H
Unit
V
V
V
V
V
V
V
MHz
0
1.0
+0.5
4.0
Note
When Transfer gate clock high level (V
φ
TG1H
to V
φ
TG3H
) is higher than Shift register clock high level (V
φ
1H
), Image
lag can increase.
4
Data Sheet S14583EJ1V0DS00
µ
PD3777
ELECTRICAL CHARACTERISTICS
T
A
= +25
°C,
V
OD
= 12 V, data rate (f
φ
RB
) = 1 MHz, storage time = 5.5 ms, input signal clock = 5 V
p-p
,
light source : 3200 K halogen lamp + C−500S (infrared cut filter, t = 1 mm) + HA−50 (heat absorbing filter, t = 3 mm)
Parameter
Saturation voltage
Saturation exposure
Red
Green
Blue
Photo response non-uniformity
Average dark signal
Dark signal non-uniformity
Power consumption
Output impedance
Response
Red
Green
Blue
Image lag
Offset level
Note 1
Note 2
Symbol
V
sat
SER
SEG
SEB
PRNU
ADS
DSNU
P
W
Z
O
R
R
R
G
R
B
IL
V
OS
t
d
TTE
RI
Red
Green
Blue
Test Conditions
MIN.
2.0
TYP.
2.5
0.420
0.429
0.739
MAX.
−
Unit
V
lx•s
lx•s
lx•s
V
OUT
= 1.0 V
Light shielding
Light shielding
6
0.2
1.5
360
0.5
4.15
4.07
2.36
5.94
5.82
3.38
2.0
4.0
5.5
50
92
0
98
1.0
630
540
460
20
2.0
5.0
540
1
7.72
7.57
4.39
7.0
7.0
%
mV
mV
mW
kΩ
V/lx•s
V/lx•s
V/lx•s
%
V
ns
%
V
OUT
= 1.0 V
Output fall delay time
V
OUT
= 1.0 V
V
OUT
= 1.0 V, data rate = 4 MHz
V
OUT
= 1.0 V
Total transfer efficiency
Register imbalance
Response peak
4.0
%
nm
nm
nm
times
times
Dynamic range
Note 1
DR1
DR2
V
sat
/DSNU
V
sat
/
σ
Light shielding
Light shielding
−1000
−
1666
2500
−300
1.0
+500
−
Reset feed-through noise
Random noise
RFTN
mV
mV
σ
Notes 1.
Refer to
TIMING CHART 2.
.
2.
When each fall time of
φ
1L and
φ
2L (t2’, t1’) is the TYP value (refer to
TIMING CHART 2).
Data Sheet S14583EJ1V0DS00
5
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