DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD3768
7500 PIXELS
×
3 COLOR CCD LINEAR IMAGE SENSOR
DESCRIPTION
The
µ
PD3768 is a high-speed and high sensitive color CCD (Charge Coupled Device) linear image sensor which
changes optical images to electrical signal and has the function of color separation.
The
µ
PD3768 has 3 rows of 7500 pixels, and it is a 2-output/color type CCD sensor with 2 rows/color of charge
transfer register, which transfers the photo signal electrons of 7500 pixels separately in odd and even pixels.
Therefore, it is suitable for 600 dpi/A3 high-speed color digital copiers, color scanners and so on.
FEATURES
•
Valid photocell
•
Photocell pitch
•
Line spacing
•
Color filter
•
Resolution
•
Data rate
•
Output type
•
Power supply
•
On-chip circuits
: 7500 pixels
×
3
: 9.325
µ
m
: 37.3
µ
m (4 lines) Red line - Green line, Green line - Blue line
: Primary colors (red, green and blue), pigment filter (with light resistance 10 lx•hour)
: 24 dot/mm A3 (297
×
420 mm) size (shorter side)
: 44 MHz MAX. (22 MHz/1 output)
: 2 outputs in phase/color
: +10 V
: Reset feed-through level clamp circuits
Voltage amplifiers
7
•
Drive clock level : CMOS output under 5 V operation
ORDERING INFORMATION
Part Number
Package
CCD linear image sensor 36-pin ceramic DIP (CERDIP) (15.24 mm (600))
µ
PD3768D
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S15418EJ2V0DS00 (2nd edition)
Date Published September 2002 NS CP (K)
Printed in Japan
The mark
shows major revised points.
2001
µ
PD3768
BLOCK DIAGRAM
φ
CP
φ
2L
φ
20
GND
16
φ
1B
φ
2A
30
29
28
23
24
V
OD
31
V
OUT
2
(Blue, even)
32
D128
CCD analog shift register
Transfer gate
S7499
S7500
D129
D140
D27
GND
V
OUT
1
(Blue, odd)
GND
33
.....
S1
S2
Photocell
(Blue)
.....
22
φ
TG1
(Blue)
Transfer gate
34
35
CCD analog shift register
Transfer gate
S7499
S7500
D128
D129
S1
S2
CCD analog shift register
V
OUT
3
36
(Green, odd)
D27
.....
.....
D140
Photocell
(Green)
21
φ
TG2
(Green)
V
OUT
4
1
(Green, even)
GND
V
OUT
6
(Red, even)
2
3
D128
Transfer gate
CCD analog shift register
CCD analog shift register
Transfer gate
S7499
S7500
D129
S1
S2
D140
D27
GND
4
.....
Photocell
(Red)
.....
15
φ
TG3
(Red)
Transfer gate
V
OUT
5
(Red, odd)
5
CCD analog shift register
6
V
OD
7
φ
R
8
φ
2L
9
φ
10
13
φ
1A
14
φ
2B
2
Data Sheet S15418EJ2V0DS
µ
PD3768
PIN CONFIGURATION (Top View)
CCD linear image sensor 36-pin ceramic DIP (CERDIP) (15.24 mm (600))
•
µ
PD3768D
Output signal 4 (Green, even) V
OUT
4 1
Ground
GND 2
36 V
OUT
3
35 GND
Output signal 3 (Green, odd)
Ground
Output signal 1 (Blue, odd)
Ground
Output signal 2 (Blue, even)
Output unit drain voltage
Reset feed-through level
clamp clock
Last stage shift register clock
Shift register clock 20
1
1
Output signal 6 (Red, even) V
OUT
6 3
Ground
GND 4
1
Blue
34 V
OUT
1
33 GND
32 V
OUT
2
31 V
OD
30
φ
CP
29
φ
2L
28
φ
20
Output signal 5 (Red, odd) V
OUT
5 5
Output unit drain voltage
Reset gate clock
Last stage shift register clock
Shift register clock 10
V
OD
6
φ
R 7
φ
2L 8
φ
10 9
No connection
No connection
No connection
Shift register clock 1A
Shift register clock 2B
Green
Red
NC 10
NC 11
NC 12
27 NC
26 NC
25 NC
24
φ
2A
23
φ
1B
22
φ
TG1
No connection
No connection
No connection
Shift register clock 2A
Shift register clock 1B
Transfer gate clock 1 (for Blue)
Transfer gate clock 2 (for Green)
No connection
No connection
φ
1A 13
φ
2B 14
Transfer gate clock 3 (for Red)
φ
TG3 15
7500
7500
7500
Ground
No connection
No connection
GND 16
NC 17
NC 18
21
φ
TG2
20 NC
19 NC
Caution
Connect the No connection pins (NC) to GND.
PHOTOCELL STRUCTURE DIAGRAM
PHOTOCELL ARRAY STRUCTURE DIAGRAM
(Line spacing)
9.325
µ
m
6.325
µ
m
3
µ
m
Channel stopper
9.325
µ
m
Blue photocell array
4 lines
(37.3
µ
m)
Green photocell array
4 lines
(37.3
µ
m)
Aluminum
shield
9.325
µ
m
9.325
µ
m
Red photocell array
Data Sheet S15418EJ2V0DS
3
µ
PD3768
ABSOLUTE MAXIMUM RATINGS (T
A
=
+
25°C)
°
Parameter
Output drain voltage
Shift register clock voltage
Last gate shift register clock voltage
Reset gate clock voltage
Clamp clock voltage
Transfer gate clock voltage
Operating ambient temperature
Note
Storage temperature
V
OD
V
φ
1
, V
φ
2
V
φ
2L
V
φ
R
V
φ
CP
V
φ
TG1
to V
φ
TG3
T
A
T
stg
Symbol
Ratings
−0.3
to
+12
−0.3
to
+8
−0.3
to
+8
−0.3
to
+8
−0.3
to
+8
−0.3
to
+8
−25
to
+60
−40
to
+100
Unit
V
V
V
V
V
V
°C
°C
Note
Use at the condition without dew condensation.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (T
A
=
+
25°C)
°
Parameter
Output drain voltage
Shift register clock high level
Shift register clock low level
Last gate shift register clock high level
Last gate shift register clock low level
Reset gate clock high level
Reset gate clock low level
Clamp clock high level
Clamp clock low level
Transfer gate clock high level
Transfer gate clock low level
Data rate
V
OD
V
φ
1H
, V
φ
2H
V
φ
1L
, V
φ
2L
V
φ
2LH
V
φ
2LL
V
φ
RH
V
φ
RL
V
φ
CPH
V
φ
CPL
V
φ
TG1H
to V
φ
TG3H
V
φ
TG1L
to V
φ
TG3L
2f
φ
R
Symbol
Min.
9.5
4.5
−0.3
4.5
−0.3
4.5
−0.3
4.5
−0.3
4.5
−0.3
1
Typ.
10.0
5.0
0
5.0
0
5.0
0
5.0
0
V
φ
1H
0
2
Note
Max.
10.5
5.5
+0.5
5.5
+0.5
5.5
+0.5
5.5
+0.5
V
φ
1H
Note
Unit
V
V
V
V
V
V
V
V
V
V
V
MHz
+0.5
44
Note
When Transfer gate clock high level (V
φ
TG1H
to V
φ
TG3H
) is higher than Shift register clock high level (V
φ
1H
),
Image lag can increase.
4
Data Sheet S15418EJ2V0DS
µ
PD3768
ELECTRICAL CHARACTERISTICS
T
A
=
+25°C,
V
OD
= 10 V, f
φ
R
= 1 MHz, data rate = 2 MHz, storage time = 10 ms, input signal clock = 5 V
p-p
,
light source (except Response1) : 2950 K halogen lamp
+
CM-500S (infrared cut filter, t = 1 mm)
Parameter
Saturation voltage
Saturation exposure
Red
Green
Blue
Photo response non-uniformity
Photo response non-uniformity
at low illumination
Average dark signal
ADS
Light shielding, data rate = 2 MHz,
storage time = 10 ms
Dark signal non-uniformity
DSNU
Light shielding, data rate = 2 MHz,
storage time = 10 ms
Power consumption
Output impedance
Response1
Red
Green
Blue
Response2
Red
Green
Blue
Image lag
Image lag color difference
Image lag O/E
Offset level
Note 1
Note 2
Symbol
V
sat
SER
SEG
SEB
PRNU
PRNU2
Test Conditions
2950 K halogen lamp
+
CM-500S
Min.
1.5
−
−
−
−
−
−
−
−
−
Typ.
2.0
0.14
0.13
0.26
6.0
6.0
Max.
−
−
−
−
18.0
18.0
Unit
V
lx•s
lx•s
lx•s
%
%
V
OUT
= 1.0 V
V
OUT
= 0.1 V
1.0
5.0
mV
3.0
12.0
mV
P
W
Z
O
R
R
R
G
R
B
R
R
R
G
R
B
IL
IL-DIF
IL-O/E
V
OS
t
d
RI
TTE
Red
Green
Blue
V
OUT
= 1.0 V
V
OUT
= 1.0 V, f
φ
R
= 22 MHz
V
OUT
= 500 mV
V
OUT
= 500 mV
V
OUT
= 500 mV
2950 K halogen lamp
+
CM-500S
3200 K halogen lamp
+
C-500S
+
HA-50
700
0.2
22.0
18.0
8.0
14.0
15.3
7.6
40
5
10
4.5
14
0
98
630
540
445
666
870
−200
2.3
900
0.4
28.6
23.4
10.4
18.2
19.9
9.9
80
20
30
5.2
−
5
−
−
−
−
−
−
+500
−
mW
kΩ
V/lx•s
V/lx•s
V/lx•s
V/lx•s
V/lx•s
V/lx•s
mV
mV
mV
V
ns
%
%
nm
nm
nm
times
times
mV
mV
15.4
12.6
5.6
9.8
10.7
5.3
−
−
−
3.8
−
−
94
−
−
−
−
−
−1000
−
Output fall delay time
Register imbalance
Total transfer efficiency
Response peak
Dynamic range
DR1
DR2
V
sat
/DSNU
V
sat
/
σ
dark
Light shielding
Bit clamp, t17 = 10 ns
Reset feed-through noise
Light shielding random noise
RFTN
σ
dark
Notes 1.
Refer to
TIMING CHART 2
and
TIMING CHART 4.
2.
t
d
is defined as periods from 10% of
φ
2L to 10% of V
OUT
1 to V
OUT
6 (refer to
APPLICATION CURCUIT
EXAMPLE).
Data Sheet S15418EJ2V0DS
5
stm32/stm8
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